Mercurial > pub > dyncall > dyncall
annotate doc/manual/callconvs/callconv_arm32.tex @ 277:703d102cb580
- doc fix in callconv appendix
| author | Tassilo Philipp |
|---|---|
| date | Sun, 04 Mar 2018 17:18:38 +0100 |
| parents | 8402121e1737 |
| children | 276eb8c87aa0 |
| rev | line source |
|---|---|
| 0 | 1 % |
| 117 | 2 % Copyright (c) 2007,2010 Daniel Adler <dadler@uni-goettingen.de>, |
| 0 | 3 % Tassilo Philipp <tphilipp@potion-studios.com> |
| 4 % | |
| 5 % Permission to use, copy, modify, and distribute this software for any | |
| 6 % purpose with or without fee is hereby granted, provided that the above | |
| 7 % copyright notice and this permission notice appear in all copies. | |
| 8 % | |
| 9 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| 10 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| 11 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| 12 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| 13 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| 14 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| 15 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| 16 % | |
| 17 | |
| 18 % ================================================== | |
| 19 % ARM32 | |
| 20 % ================================================== | |
| 21 \subsection{ARM32 Calling Convention} | |
| 22 | |
| 23 \paragraph{Overview} | |
| 24 | |
| 117 | 25 The ARM32 family of processors is based on the Advanced RISC Machines (ARM) |
| 26 processor architecture (32 bit RISC). | |
| 0 | 27 The word size is 32 bits (and the programming model is LLP64).\\ |
| 28 Basically, this family of microprocessors can be run in 2 major modes:\\ | |
| 29 \\ | |
| 77 | 30 \begin{tabular*}{0.95\textwidth}{2 B} |
| 0 | 31 Mode & Description\\ |
| 32 \hline | |
| 33 {\bf ARM} & 32bit instruction set\\ | |
| 34 {\bf THUMB} & compressed instruction set using 16bit wide instruction encoding\\ | |
| 76 | 35 \end{tabular*} |
| 0 | 36 \\ |
| 37 \\ | |
| 95 | 38 For more details, take a look at the ARM-THUMB Procedure Call Standard (ATPCS) \cite{ATPCS}, the Procedure Call Standard for the ARM Architecture (AAPCS) \cite{AAPCS}, as well as the Debian ARM EABI port wiki \cite{armeabi}.\\ |
| 173 | 39 \\ |
| 0 | 40 \paragraph{\product{dyncall} support} |
| 41 | |
| 42 Currently, the \product{dyncall} library supports the ARM and THUMB mode of the ARM32 family (ATPCS \cite{ATPCS} and EABI \cite{armeabi}), excluding manually triggered ARM-THUMB interworking calls. Although it's quite possible that the current implementation runs on other ARM processor families as well, please note that only the ARMv4t family has been thoroughly tested at the time of writing. Please report if the code runs on other ARM families, too.\\ | |
| 43 It is important to note, that dyncall supports the ARM architecture calling convention variant {\bf with floating point hardware disabled} (meaning that the FPA and the VFP (scalar mode) procedure call standards are not supported). | |
| 44 This processor family features some instruction sets accelerating DSP and multimedia application like the ARM Jazelle Technology (direct Java bytecode execution, providing acceleration for some bytecodes while calling software code for others), etc. that are not supported by the dyncall library.\\ | |
| 45 | |
| 46 | |
| 47 \subsubsection{ATPCS ARM mode} | |
| 48 | |
| 49 | |
| 50 \paragraph{Registers and register usage} | |
| 51 | |
| 52 In ARM mode, the ARM32 processor has sixteen 32 bit general purpose registers, namely r0-r15:\\ | |
| 53 \\ | |
| 54 \begin{table}[h] | |
| 77 | 55 \begin{tabular*}{0.95\textwidth}{3 B} |
| 0 | 56 Name & Brief description\\ |
| 57 \hline | |
| 58 {\bf r0} & parameter 0, scratch, return value\\ | |
| 59 {\bf r1} & parameter 1, scratch, return value\\ | |
| 60 {\bf r2-r3} & parameters 2 and 3, scratch\\ | |
| 61 {\bf r4-r10} & permanent\\ | |
| 62 {\bf r11} & frame pointer, permanent\\ | |
| 63 {\bf r12} & scratch\\ | |
| 64 {\bf r13} & stack pointer, permanent\\ | |
| 65 {\bf r14} & link register, permanent\\ | |
| 66 {\bf r15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\ | |
| 76 | 67 \end{tabular*} |
| 0 | 68 \caption{Register usage on arm32} |
| 69 \end{table} | |
| 70 | |
| 71 \paragraph{Parameter passing} | |
| 72 | |
| 73 \begin{itemize} | |
| 74 \item stack parameter order: right-to-left | |
| 75 \item caller cleans up the stack | |
| 76 \item first four words are passed using r0-r3 | |
| 77 \item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters) | |
| 78 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack | |
| 79 \item parameters \textless=\ 32 bits are passed as 32 bit words | |
| 35 | 80 \item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack, although this doesn't seem to be specified in the ATPCS), with the loword coming first |
| 0 | 81 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3 |
| 82 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc... (see {\bf return values}) | |
| 83 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis) | |
| 84 \end{itemize} | |
| 85 | |
| 86 \paragraph{Return values} | |
| 87 \begin{itemize} | |
| 88 \item return values \textless=\ 32 bits use r0 | |
| 89 \item 64 bit return values use r0 and r1 | |
| 90 \item if return value is a structure, the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0 | |
| 91 \end{itemize} | |
| 92 | |
| 93 \paragraph{Stack layout} | |
| 94 | |
| 95 Stack directly after function prolog:\\ | |
| 96 | |
| 97 \begin{figure}[h] | |
| 98 \begin{tabular}{5|3|1 1} | |
| 99 \hhline{~-~~} | |
| 92 | 100 & \vdots & & \\ |
| 0 | 101 \hhline{~=~~} |
| 92 | 102 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ |
| 0 | 103 \hhline{~-~~} |
| 92 | 104 local data & & & \\ |
| 117 | 105 \hhline{~-~~} |
| 92 | 106 \mrlbrace{7}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ |
| 107 & \ldots & & \\ | |
| 108 & \ldots & & \\ | |
| 117 | 109 \hhline{~=~~} |
| 92 | 110 & r3 & \mrrbrace{4}{spill area (if needed)} & \mrrbrace{7}{current frame} \\ |
| 111 & r2 & & \\ | |
| 112 & r1 & & \\ | |
| 113 & r0 & & \\ | |
| 117 | 114 \hhline{~-~~} |
| 92 | 115 register save area (with return address) & & & \\ |
| 117 | 116 \hhline{~-~~} |
| 92 | 117 local data & & & \\ |
| 117 | 118 \hhline{~-~~} |
| 92 | 119 parameter area & \vdots & & \\ |
| 0 | 120 \hhline{~-~~} |
| 121 \end{tabular} | |
| 122 \caption{Stack layout on arm32} | |
| 123 \end{figure} | |
| 124 | |
| 125 | |
| 126 \newpage | |
| 127 | |
| 128 \subsubsection{ATPCS THUMB mode} | |
| 129 | |
| 130 | |
| 131 \paragraph{Status} | |
| 132 | |
| 133 \begin{itemize} | |
| 134 \item The ATPCS THUMB mode is untested. | |
| 135 \item Ellipse calls may not work. | |
| 136 \item C++ this calls do not work. | |
| 137 \end{itemize} | |
| 138 | |
| 139 \paragraph{Registers and register usage} | |
| 140 | |
| 141 In THUMB mode, the ARM32 processor family supports eight 32 bit general purpose registers r0-r7 and access to high order registers r8-r15:\\ | |
| 142 \\ | |
| 143 \begin{table}[h] | |
| 77 | 144 \begin{tabular*}{0.95\textwidth}{3 B} |
| 0 | 145 Name & Brief description\\ |
| 146 \hline | |
| 147 {\bf r0} & parameter 0, scratch, return value\\ | |
| 148 {\bf r1} & parameter 1, scratch, return value\\ | |
| 35 | 149 {\bf r2,r3} & parameters 2 and 3, scratch\\ |
| 0 | 150 {\bf r4-r6} & permanent\\ |
| 151 {\bf r7} & frame pointer, permanent\\ | |
| 152 {\bf r8-r11} & permanent\\ | |
| 153 {\bf r12} & scratch\\ | |
| 154 {\bf r13} & stack pointer, permanent\\ | |
| 155 {\bf r14} & link register, permanent\\ | |
| 156 {\bf r15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\ | |
| 76 | 157 \end{tabular*} |
| 0 | 158 \caption{Register usage on arm32 thumb mode} |
| 159 \end{table} | |
| 160 | |
| 161 \paragraph{Parameter passing} | |
| 162 | |
| 163 \begin{itemize} | |
| 164 \item stack parameter order: right-to-left | |
| 165 \item caller cleans up the stack | |
| 166 \item first four words are passed using r0-r3 | |
| 167 \item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters) | |
| 168 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack | |
| 169 \item parameters \textless=\ 32 bits are passed as 32 bit words | |
| 170 \item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack), although this doesn't seem to be specified in the ATPCS), with the loword coming first | |
| 171 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3 | |
| 172 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc. (see {\bf return values}) | |
| 173 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis) | |
| 174 \end{itemize} | |
| 175 | |
| 176 \paragraph{Return values} | |
| 177 \begin{itemize} | |
| 178 \item return values \textless=\ 32 bits use r0 | |
| 179 \item 64 bit return values use r0 and r1 | |
| 180 \item if return value is a structure, the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0 | |
| 181 \end{itemize} | |
| 182 | |
| 183 \paragraph{Stack layout} | |
| 184 | |
| 185 Stack directly after function prolog:\\ | |
| 186 | |
| 187 \begin{figure}[h] | |
| 188 \begin{tabular}{5|3|1 1} | |
| 189 \hhline{~-~~} | |
| 92 | 190 & \vdots & & \\ |
| 117 | 191 \hhline{~=~~} |
| 92 | 192 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ |
| 117 | 193 \hhline{~-~~} |
| 92 | 194 local data & & & \\ |
| 117 | 195 \hhline{~-~~} |
| 92 | 196 \mrlbrace{7}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ |
| 197 & \ldots & & \\ | |
| 198 & \ldots & & \\ | |
| 117 | 199 \hhline{~=~~} |
| 92 | 200 & r3 & \mrrbrace{4}{spill area (if needed)} & \mrrbrace{7}{current frame} \\ |
| 201 & r2 & & \\ | |
| 202 & r1 & & \\ | |
| 203 & r0 & & \\ | |
| 117 | 204 \hhline{~-~~} |
| 92 | 205 register save area (with return address) & & & \\ |
| 117 | 206 \hhline{~-~~} |
| 92 | 207 local data & & & \\ |
| 117 | 208 \hhline{~-~~} |
| 92 | 209 parameter area & \vdots & & \\ |
| 0 | 210 \hhline{~-~~} |
| 211 \end{tabular} | |
| 212 \caption{Stack layout on arm32 thumb mode} | |
| 213 \end{figure} | |
| 214 | |
| 215 | |
| 216 | |
| 217 \newpage | |
| 218 | |
| 219 \subsubsection{EABI (ARM and THUMB mode)} | |
| 220 | |
| 221 | |
| 222 The ARM EABI is very similar to the ABI outlined in ARM-THUMB procedure call | |
| 223 standard (ATPCS) \cite{ATPCS} - however, the EABI requires the stack to be | |
| 41 | 224 8-byte aligned at function entries, as well as for 64 bit parameters. The latter |
| 225 are aligned on 8-byte boundaries on the stack and 2-registers for a parameter | |
| 0 | 226 passed via register. In order to achieve such an alignment, a register might |
| 227 have to be skipped for parameters passed via registers, or 4-bytes on the stack | |
| 35 | 228 for parameters passed via the stack. Refer to the Debian ARM EABI port wiki |
| 173 | 229 for more information \cite{armeabi}.\\ |
| 230 \\ | |
| 0 | 231 \paragraph{Status} |
| 232 | |
| 233 \begin{itemize} | |
| 234 \item The EABI THUMB mode is tested and works fine (contrary to the ATPCS). | |
| 235 \item Ellipse calls do not work. | |
| 236 \item C++ this calls do not work. | |
| 237 \end{itemize} | |
| 238 | |
| 239 \newpage | |
| 240 | |
| 241 \subsubsection{ARM on Apple's iOS (Darwin) Platform} | |
| 242 | |
| 243 | |
| 244 The iOS runs on ARMv6 (iOS 2.0) and ARMv7 (iOS 3.0) architectures. | |
| 173 | 245 Typically code is compiled in Thumb mode.\\ |
| 246 \\ | |
| 0 | 247 \paragraph{Register usage} |
| 248 | |
| 249 \begin{table}[h] | |
| 77 | 250 \begin{tabular*}{0.95\textwidth}{3 B} |
| 0 | 251 Name & Brief description\\ |
| 252 \hline | |
| 253 {\bf R0} & parameter 0, scratch, return value\\ | |
| 254 {\bf R1} & parameter 1, scratch, return value\\ | |
| 35 | 255 {\bf R2,R3} & parameters 2 and 3, scratch\\ |
| 0 | 256 {\bf R4-R6} & permanent\\ |
| 257 {\bf R7} & frame pointer, permanent\\ | |
| 258 {\bf R8} & permanent\\ | |
| 259 {\bf R9} & permanent(iOS 2.0) and scratch (since iOS 3.0)\\ | |
| 260 {\bf R10-R11}& permanent\\ | |
| 261 {\bf R12} & scratch, intra-procedure scratch register (IP) used by dynamic linker\\ | |
| 262 {\bf R13} & stack pointer, permanent\\ | |
| 263 {\bf R14} & link register, permanent\\ | |
| 264 {\bf R15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\ | |
| 265 {\bf CPSR} & Program status register\\ | |
| 35 | 266 {\bf D0-D7} & scratch. aliases S0-S15, on ARMv7 also as Q0-Q3. Not accessible from Thumb mode on ARMv6.\\ |
| 267 {\bf D8-D15} & permanent, aliases S16-S31, on ARMv7 also as Q4-A7. Not accesible from Thumb mode on ARMv6.\\ | |
| 0 | 268 {\bf D16-D31}& Only available in ARMv7, aliases Q8-Q15.\\ |
| 269 {\bf FPSCR} & VFP status register.\\ | |
| 76 | 270 \end{tabular*} |
| 0 | 271 \caption{Register usage on ARM Apple iOS} |
| 272 \end{table} | |
| 273 | |
| 274 The ABI is based on the AAPCS but with some important differences listed below: | |
| 275 | |
| 276 \begin{itemize} | |
| 277 \item R7 instead of R11 is used as frame pointer | |
| 278 \item R9 is scratch since iOS 3.0, was preserved before. | |
| 279 \end{itemize} | |
| 280 | |
| 34 | 281 |
| 282 \subsubsection{ARM hard float (armhf)} | |
| 283 | |
| 284 | |
| 35 | 285 Most debian-based Linux systems on ARMv7 (or ARMv6 with FPU) platforms use a calling convention referred to |
| 41 | 286 as armhf, using 16 32-bit floating point registers of the FPU of the VFPv3-D16 extension to the ARM architecture. |
| 35 | 287 The instruction set used for armhf is Thumb-2. Refer to the debian wiki for more information \cite{armhf}. |
| 288 | |
| 173 | 289 Code is little-endian, rest is similar to EABI with an 8-byte aligned stack, etc..\\ |
| 290 \\ | |
| 34 | 291 \paragraph{Register usage} |
| 292 | |
| 293 \begin{table}[h] | |
| 77 | 294 \begin{tabular*}{0.95\textwidth}{3 B} |
| 34 | 295 Name & Brief description\\ |
| 296 \hline | |
|
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297 {\bf R0} & parameter 0, scratch, non floating point return value\\ |
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298 {\bf R1} & parameter 1, scratch, non floating point return value\\ |
| 35 | 299 {\bf R2,R3} & parameters 2 and 3, scratch\\ |
| 300 {\bf R4,R5} & permanent\\ | |
| 301 {\bf R6} & scratch\\ | |
| 302 {\bf R7} & frame pointer, permanent\\ | |
| 303 {\bf R8} & permanent\\ | |
| 304 {\bf R9,R10} & scratch\\ | |
| 305 {\bf R11} & permanent\\ | |
| 306 {\bf R12} & scratch, intra-procedure scratch register (IP) used by dynamic linker\\ | |
| 307 {\bf R13} & stack pointer, permanent\\ | |
| 308 {\bf R14} & link register, permanent\\ | |
| 309 {\bf R15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\ | |
| 310 {\bf CPSR} & Program status register\\ | |
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311 {\bf S0} & floating point argument, floating point return value, single precision\\ |
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312 {\bf D0} & floating point argument, floating point return value, double precision, aliases S0-S1, \\ |
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313 {\bf S1-S15} & floating point arguments, single precision\\ |
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314 {\bf D1-D7} & aliases S2-S15, floating point arguments, double precision\\ |
| 35 | 315 {\bf FPSCR} & VFP status register.\\ |
| 76 | 316 \end{tabular*} |
| 34 | 317 \caption{Register usage on armhf} |
| 318 \end{table} | |
| 319 | |
| 35 | 320 \paragraph{Parameter passing} |
| 321 | |
| 322 \begin{itemize} | |
| 323 \item stack parameter order: right-to-left | |
| 324 \item caller cleans up the stack | |
| 325 \item first four non-floating-point words are passed using r0-r3 | |
| 51 | 326 \item out of those, 64bit parameters use 2 registers, either r0,r1 or r2,r3 (skipped registers are left unused) |
| 41 | 327 \item first 16 single-precision, or 8 double-precision arguments are passed via s0-s15 or d0-d7, respectively (note that since s and d registers are aliased, already used ones are skipped) |
| 35 | 328 \item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters) |
| 47 | 329 \item note that as soon one floating point parameter is passed via the stack, subsequent single precision floating point parameters are also pushed onto the stack even if there are still free S* registers |
| 51 | 330 \item float and double vararg function parameters (no matter if in ellipsis part of function, or not) are passed like int or long long parameters, vfp registers aren't used |
| 50 | 331 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words (for first 4 integer arguments) to a reserved stack area adjacent to the other parameters on the stack |
| 35 | 332 \item parameters \textless=\ 32 bits are passed as 32 bit words |
| 333 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3 @@@?check doc | |
| 334 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc. (see {\bf return values}) | |
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335 \item callee spills, caller reserves spill area space, though |
| 35 | 336 \end{itemize} |
| 337 | |
| 338 \paragraph{Return values} | |
| 339 \begin{itemize} | |
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340 \item non floating point return values \textless=\ 32 bits use r0 |
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341 \item non floating point 64-bit return values use r0 and r1 |
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342 \item single precision floating point return value uses s0 |
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343 \item double precision floating point return value uses d0 |
| 35 | 344 \item if return value is a structure, the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0 |
| 345 \end{itemize} | |
| 346 | |
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347 \paragraph{Stack layout} |
| 35 | 348 |
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349 Stack directly after function prolog:\\ |
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350 |
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351 \begin{figure}[h] |
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352 \begin{tabular}{5|3|1 1} |
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353 \hhline{~-~~} |
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354 & \vdots & & \\ |
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355 \hhline{~=~~} |
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356 register save area & \hspace{4cm} & & \mrrbrace{6}{caller's frame} \\ |
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357 \hhline{~-~~} |
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358 local data & & & \\ |
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359 \hhline{~-~~} |
| 277 | 360 \mrlbrace{4}{parameter area} & r0-r3 & \mrrbrace{1}{spill area (if needed)} & \\ |
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361 \hhline{~-~~} |
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362 & \ldots & \mrrbrace{3}{stack parameters} & \\ |
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363 & \ldots & & \\ |
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364 & \ldots & & \\ |
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365 \hhline{~=~~} |
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366 register save area (with return address) & & & \mrrbrace{3}{current frame} \\ |
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367 \hhline{~-~~} |
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368 local data & & & \\ |
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369 \hhline{~-~~} |
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370 parameter area & \vdots & & \\ |
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371 \hhline{~-~~} |
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372 \end{tabular} |
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373 \caption{Stack layout on arm32 armhf} |
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374 \end{figure} |
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375 |
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376 |
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377 \newpage |
| 35 | 378 |
| 34 | 379 |
| 0 | 380 \subsubsection{Architectures} |
| 381 | |
| 382 The ARM architecture family contains several revisions with capabilities and | |
| 117 | 383 extensions (such as thumb-interworking, more vector registers, ...) |
| 384 The following table sums up the most important properties of the various | |
| 34 | 385 architecture standards, from a calling convention perspective. |
| 0 | 386 |
| 387 % iPhone 3GS : ARM Cortex-A8 | |
| 388 % Nintendo DS: ARM 7 and ARM 9 | |
| 389 % ARM 7: ARMv4T | |
| 390 % ARM 9: ARMv4T, HTC Wizard | |
| 34 | 391 % Cortex-*: ARMv7, Raspberry Pi 2, ... |
| 0 | 392 |
| 393 \begin{table}[h] | |
| 77 | 394 \begin{tabular*}{0.95\textwidth}{lll} |
| 0 | 395 Arch & Platforms & Details \\ |
| 396 \hline | |
| 397 ARMv4 & & \\ | |
| 398 ARMv4T & ARM 7, ARM 9, Neo FreeRunner (OpenMoko) & \\ | |
| 34 | 399 ARMv5 & ARM 9E & BLX instruction available \\ |
| 0 | 400 ARMv6 & & No vector registers available in thumb \\ |
| 117 | 401 ARMv7 & iPod touch, iPhone 3GS/4, Raspberry Pi 2 & VFP throughout available, armhf calling convention on some platforms \\ |
| 402 ARMv8 & iPhone 6 and higher & 64bit support \\ | |
| 76 | 403 \end{tabular*} |
| 0 | 404 \caption{Overview of ARM Architecture, Platforms and Details} |
| 405 \end{table} | |
| 406 | |
| 407 \newpage | |
| 408 |