--- a/doc/manual/callconvs/callconv_arm32.tex	Tue Dec 15 11:19:57 2015 +0100
+++ b/doc/manual/callconvs/callconv_arm32.tex	Tue Dec 15 14:40:19 2015 +0100
@@ -82,7 +82,7 @@
 \item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters)
 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack
 \item parameters \textless=\ 32 bits are passed as 32 bit words
-\item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack), although this doesn't seem to be specified in the ATPCS), with the loword coming first
+\item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack, although this doesn't seem to be specified in the ATPCS), with the loword coming first
 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3
 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc... (see {\bf return values})
 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis)
@@ -152,7 +152,7 @@
 \hline
 {\bf r0}     & parameter 0, scratch, return value\\
 {\bf r1}     & parameter 1, scratch, return value\\
-{\bf r2-r3}  & parameters 2 and 3, scratch\\
+{\bf r2,r3}  & parameters 2 and 3, scratch\\
 {\bf r4-r6}  & permanent\\
 {\bf r7}     & frame pointer, permanent\\
 {\bf r8-r11} & permanent\\
@@ -180,7 +180,6 @@
 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis)
 \end{itemize}
 
-
 \paragraph{Return values}
 \begin{itemize}
 \item return values \textless=\ 32 bits use r0
@@ -233,7 +232,8 @@
 are aligned on 8-byte boundaries on the stack and 2-registers for parameters
 passed via register. In order to achieve such an alignment, a register might
 have to be skipped for parameters passed via registers, or 4-bytes on the stack
-for parameters passed via the stack. Refer to the Debian ARM EABI port wiki for more information \cite{armeabi}.
+for parameters passed via the stack. Refer to the Debian ARM EABI port wiki
+for more information \cite{armeabi}.
 
 
 \paragraph{Status}
@@ -261,7 +261,7 @@
 \hline
 {\bf R0}     & parameter 0, scratch, return value\\
 {\bf R1}     & parameter 1, scratch, return value\\
-{\bf R2-R3}  & parameters 2 and 3, scratch\\
+{\bf R2,R3}  & parameters 2 and 3, scratch\\
 {\bf R4-R6}  & permanent\\
 {\bf R7}     & frame pointer, permanent\\
 {\bf R8}     & permanent\\
@@ -272,8 +272,8 @@
 {\bf R14}    & link register, permanent\\
 {\bf R15}    & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
 {\bf CPSR}   & Program status register\\
-{\bf D0-D7}  & scratch. aliases S0-S15, on ARMv7 alsa as Q0-Q3. Not accessible from Thumb mode on ARMv6.\\
-{\bf D8-D15} & permanent, aliases S16-S31, on ARMv7 alsa as Q4-A7. Not accesible from Thumb mode on ARMv6.\\
+{\bf D0-D7}  & scratch. aliases S0-S15, on ARMv7 also as Q0-Q3. Not accessible from Thumb mode on ARMv6.\\
+{\bf D8-D15} & permanent, aliases S16-S31, on ARMv7 also as Q4-A7. Not accesible from Thumb mode on ARMv6.\\
 {\bf D16-D31}& Only available in ARMv7, aliases Q8-Q15.\\
 {\bf FPSCR}  & VFP status register.\\
 \hline
@@ -292,9 +292,11 @@
 \subsubsection{ARM hard float (armhf)}
 
 
-Most debian-based Linux systems on ARMv7 platforms use a calling convention referred to as armhf, using
-16 64-bit floating point registers of the FPU of the VFPv3-D16 extension to the ARM architecture. Code
-is using the Thumb-2 instruction set.
+Most debian-based Linux systems on ARMv7 (or ARMv6 with FPU) platforms use a calling convention referred to
+as armhf, using 16 64-bit floating point registers of the FPU of the VFPv3-D16 extension to the ARM architecture.
+The instruction set used for armhf is Thumb-2. Refer to the debian wiki for more information \cite{armhf}.
+
+Code is little-endian, rest is similar to EABI, 8-byte aligned stack, etc..
 
 \paragraph{Register usage}
 
@@ -303,12 +305,52 @@
 \hline
 Name         & Brief description\\
 \hline
-... tbd
+{\bf R0}     & parameter 0, scratch, return value\\
+{\bf R1}     & parameter 1, scratch, return value\\
+{\bf R2,R3}  & parameters 2 and 3, scratch\\
+{\bf R4,R5}  & permanent\\
+{\bf R6}     & scratch\\
+{\bf R7}     & frame pointer, permanent\\
+{\bf R8}     & permanent\\
+{\bf R9,R10} & scratch\\
+{\bf R11}    & permanent\\
+{\bf R12}    & scratch, intra-procedure scratch register (IP) used by dynamic linker\\
+{\bf R13}    & stack pointer, permanent\\
+{\bf R14}    & link register, permanent\\
+{\bf R15}    & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
+{\bf CPSR}   & Program status register\\
+{\bf S0-S15} & floating point arguments, single precision\\
+{\bf D0-D7}  & aliases S0-S15, floating point arguments, double precision\\
+{\bf FPSCR}  & VFP status register.\\
 \hline
 \end{tabular}
 \caption{Register usage on armhf}
 \end{table}
 
+\paragraph{Parameter passing}
+
+\begin{itemize}
+\item stack parameter order: right-to-left
+\item caller cleans up the stack
+\item first four non-floating-point words are passed using r0-r3
+\item first 16 single-precision, or 8 double-precision arguments are passed via s0-s15 or d0-d7, respectively
+\item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters)
+\item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack @@@?check doc
+\item parameters \textless=\ 32 bits are passed as 32 bit words
+\item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack, although this doesn't seem to be specified in the ATPCS), with the loword coming first @@@?check doc
+\item structures and unions are passed by value, with the first four words of the parameters in r0-r3 @@@?check doc
+\item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc. (see {\bf return values})
+\end{itemize}
+
+\paragraph{Return values}
+\begin{itemize}
+\item return values \textless=\ 32 bits use r0
+\item 64 bit return values use r0 and r1
+\item if return value is a structure, the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0
+\end{itemize}
+
+
+
 
 \subsubsection{Architectures}
 

--- a/doc/manual/manual_literature.tex	Tue Dec 15 11:19:57 2015 +0100
+++ b/doc/manual/manual_literature.tex	Tue Dec 15 14:40:19 2015 +0100
@@ -117,6 +117,10 @@
 	Debian ARM EABI Port Wiki\\
 	\url{http://wiki.debian.org/ArmEabiPort}
 
+\bibitem{armhf}
+	Debian ArmHardFloatPort\\
+	\url{https://wiki.debian.org/ArmHardFloatPort}
+
 \bibitem{x64Win}
 	MSDN: x64 Software Conventions\\
 	\url{http://msdn.microsoft.com/en-us/library/ms235286\%28VS.80\%29.aspx}