--- a/doc/manual/callconvs/callconv_arm32.tex	Sun Mar 20 18:44:41 2016 +0100
+++ b/doc/manual/callconvs/callconv_arm32.tex	Mon Mar 21 01:15:37 2016 +0100
@@ -27,14 +27,14 @@
 The word size is 32 bits (and the programming model is LLP64).\\
 Basically, this family of microprocessors can be run in 2 major modes:\\
 \\
-\begin{tabular}{2 B}
+\begin{tabular*}{0.75\textwidth}{2 B}
 \hline
 Mode          & Description\\
 \hline
 {\bf ARM}     & 32bit instruction set\\
 {\bf THUMB}   & compressed instruction set using 16bit wide instruction encoding\\
 \hline
-\end{tabular}
+\end{tabular*}
 \\
 \\
 For more details, take a look at the ARM-THUMB Procedure Call Standard (ATPCS) \cite{ATPCS}, the Procedure Call Standard for the ARM Architecture (AAPCS) \cite{AAPCS}, as well as the Debian ARM EABI port wiki \cite{armeabi}.
@@ -55,7 +55,7 @@
 In ARM mode, the ARM32 processor has sixteen 32 bit general purpose registers, namely r0-r15:\\
 \\
 \begin{table}[h]
-\begin{tabular}{3 B}
+\begin{tabular*}{0.75\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -69,7 +69,7 @@
 {\bf r14}    & link register, permanent\\
 {\bf r15}    & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
 \hline
-\end{tabular}
+\end{tabular*}
 \caption{Register usage on arm32}
 \end{table}
 
@@ -146,7 +146,7 @@
 In THUMB mode, the ARM32 processor family supports eight 32 bit general purpose registers r0-r7 and access to high order registers r8-r15:\\
 \\
 \begin{table}[h]
-\begin{tabular}{3 B}
+\begin{tabular*}{0.75\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -161,7 +161,7 @@
 {\bf r14}    & link register, permanent\\
 {\bf r15}    & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
 \hline
-\end{tabular}
+\end{tabular*}
 \caption{Register usage on arm32 thumb mode}
 \end{table}
 
@@ -255,7 +255,7 @@
 \paragraph{Register usage}
 
 \begin{table}[h]
-\begin{tabular}{3 B}
+\begin{tabular*}{0.75\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -277,7 +277,7 @@
 {\bf D16-D31}& Only available in ARMv7, aliases Q8-Q15.\\
 {\bf FPSCR}  & VFP status register.\\
 \hline
-\end{tabular}
+\end{tabular*}
 \caption{Register usage on ARM Apple iOS}
 \end{table}
 
@@ -301,7 +301,7 @@
 \paragraph{Register usage}
 
 \begin{table}[h]
-\begin{tabular}{3 B}
+\begin{tabular*}{0.75\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -325,7 +325,7 @@
 {\bf D1-D7}  & aliases S2-S15, floating point arguments, double precision\\
 {\bf FPSCR}  & VFP status register.\\
 \hline
-\end{tabular}
+\end{tabular*}
 \caption{Register usage on armhf}
 \end{table}
 
@@ -372,7 +372,7 @@
 % Cortex-*: ARMv7, Raspberry Pi 2, ...
 
 \begin{table}[h]
-\begin{tabular}{lll}
+\begin{tabular*}{0.75\textwidth}{lll}
 Arch   & Platforms & Details \\
 \hline
 ARMv4  & & \\
@@ -387,7 +387,7 @@
 \hline
 ARMv8  & iPhone 6 and higher & 64bit support \\ 
 \hline
-\end{tabular}
+\end{tabular*}
 \caption{Overview of ARM Architecture, Platforms and Details}
 \end{table}