--- a/doc/manual/callconvs/callconv_arm32.tex	Mon Mar 21 01:15:37 2016 +0100
+++ b/doc/manual/callconvs/callconv_arm32.tex	Mon Mar 21 01:23:37 2016 +0100
@@ -27,7 +27,7 @@
 The word size is 32 bits (and the programming model is LLP64).\\
 Basically, this family of microprocessors can be run in 2 major modes:\\
 \\
-\begin{tabular*}{0.75\textwidth}{2 B}
+\begin{tabular*}{0.95\textwidth}{2 B}
 \hline
 Mode          & Description\\
 \hline
@@ -55,7 +55,7 @@
 In ARM mode, the ARM32 processor has sixteen 32 bit general purpose registers, namely r0-r15:\\
 \\
 \begin{table}[h]
-\begin{tabular*}{0.75\textwidth}{3 B}
+\begin{tabular*}{0.95\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -146,7 +146,7 @@
 In THUMB mode, the ARM32 processor family supports eight 32 bit general purpose registers r0-r7 and access to high order registers r8-r15:\\
 \\
 \begin{table}[h]
-\begin{tabular*}{0.75\textwidth}{3 B}
+\begin{tabular*}{0.95\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -255,7 +255,7 @@
 \paragraph{Register usage}
 
 \begin{table}[h]
-\begin{tabular*}{0.75\textwidth}{3 B}
+\begin{tabular*}{0.95\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -301,7 +301,7 @@
 \paragraph{Register usage}
 
 \begin{table}[h]
-\begin{tabular*}{0.75\textwidth}{3 B}
+\begin{tabular*}{0.95\textwidth}{3 B}
 \hline
 Name         & Brief description\\
 \hline
@@ -372,7 +372,7 @@
 % Cortex-*: ARMv7, Raspberry Pi 2, ...
 
 \begin{table}[h]
-\begin{tabular*}{0.75\textwidth}{lll}
+\begin{tabular*}{0.95\textwidth}{lll}
 Arch   & Platforms & Details \\
 \hline
 ARMv4  & & \\