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annotate doc/manual/callconvs/callconv_ppc32.tex @ 530:585dcb68f55d
- more doc and disas examples for x86 fastcall and non-trivial aggregates
author | Tassilo Philipp |
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date | Sat, 16 Apr 2022 12:10:02 +0200 |
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0 | 1 %////////////////////////////////////////////////////////////////////////////// |
2 % | |
478 | 3 % Copyright (c) 2007-2022 Daniel Adler <dadler@uni-goettingen.de>, |
0 | 4 % Tassilo Philipp <tphilipp@potion-studios.com> |
5 % | |
6 % Permission to use, copy, modify, and distribute this software for any | |
7 % purpose with or without fee is hereby granted, provided that the above | |
8 % copyright notice and this permission notice appear in all copies. | |
9 % | |
10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
17 % | |
18 %////////////////////////////////////////////////////////////////////////////// | |
19 | |
20 % ================================================== | |
21 % PowerPC 32 | |
22 % ================================================== | |
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23 \subsection{PowerPC (32bit) Calling Conventions} |
0 | 24 |
25 \paragraph{Overview} | |
26 | |
27 \begin{itemize} | |
28 \item Word size is 32 bits | |
29 \item Big endian (MSB) and litte endian (LSB) operating modes. | |
30 \item Processor operates on floats in double precision floating point arithmetc (IEEE-754) values directly (single precision is converted on the fly) | |
331 | 31 \item Apple macos/Mac OS X/Darwin PPC is specified in "Mac OS X ABI Function Call Guide"\cite{ppcMacOSX}. It uses Big Endian (MSB) |
32 \item Linux PPC 32-bit ABI is specified in "LSB for PPC"\cite{ppc32LSB} which is based on "System V ABI". It uses Big Endian (MSB) | |
33 \item PowerPC EABI is defined in the "PowerPC Embedded Application Binary Interface 32-Bit Implementation"\cite{ppceabi} | |
34 \item There is also the "PowerOpen ABI"\cite{poabi}, a nearly identical version of it is used in AIX % more info: http://www.ingallegri.com/public/ppc.html | |
0 | 35 \end{itemize} |
36 | |
37 \paragraph{\product{dyncall} support} | |
38 | |
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39 \product{Dyncall} and \product{dyncallback} are supported for PowerPC (32bit) |
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40 Big Endian (MSB), for Darwin's and System V's calling convention.\\ |
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41 \product{Dyncall} can also be used to issue syscalls by using the syscall |
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42 number as target parameter and selecting the correct mode. |
0 | 43 |
44 | |
45 \subsubsection{Mac OS X/Darwin} | |
46 | |
47 \paragraph{Registers and register usage} | |
48 | |
49 \begin{table}[h] | |
77 | 50 \begin{tabular*}{0.95\textwidth}{3 B} |
0 | 51 Name & Brief description\\ |
52 \hline | |
53 {\bf gpr0} & scratch\\ | |
54 {\bf gpr1} & stack pointer\\ | |
55 {\bf gpr2} & scratch\\ | |
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56 {\bf gpr3,gpr4} & return value, parameter 0 and 1 for integer or pointer, scratch\\ |
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57 {\bf gpr5-gpr10} & parameter 2-7 for integer or pointer parameters, scratch\\ |
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58 {\bf gpr11} & preserve\\ |
0 | 59 {\bf gpr12} & branch target for dynamic code generation\\ |
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60 {\bf gpr13-31} & preserve\\ |
0 | 61 {\bf fpr0} & scratch\\ |
238 | 62 {\bf fpr1} & floating point return value, floating point parameter 0 (always double precision)\\ |
63 {\bf fpr2-fpr13} & floating point parameters 1-12 (always double precision)\\ | |
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64 {\bf fpr14-fpr31} & preserve\\ |
0 | 65 {\bf v0-v1} & scratch\\ |
66 {\bf v2-v13} & vector parameters\\ | |
67 {\bf v14-v19} & scratch\\ | |
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68 {\bf v20-v31} & preserve\\ |
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69 {\bf lr} & link-register, scratch\\ |
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70 {\bf ctr} & count-register, scratch\\ |
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71 {\bf cr0-cr7} & conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\ |
76 | 72 \end{tabular*} |
0 | 73 \caption{Register usage on Darwin PowerPC 32-Bit} |
74 \end{table} | |
75 | |
76 \paragraph{Parameter passing} | |
77 | |
78 \begin{itemize} | |
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79 \item stack grows down |
238 | 80 \item stack parameter order: right-to-left |
81 \item caller cleans up the stack | |
0 | 82 \item the first 8 integer parameters are passed in registers gpr3-gpr10 |
331 | 83 \item the first 13 floating point parameters are passed in registers fpr1-fpr13 |
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84 \item 64 bit arguments are passed as if they were two 32 bit arguments, without skipping registers for alignment (this means passing half via a register and half via the stack is allowed) |
0 | 85 \item if a float parameter is passed via a register, gpr registers are skipped for subsequent integer parameters (based on the size of |
86 the float - 1 register for single precision and 2 for double precision floating point values) | |
87 \item the caller pushes subsequent parameters onto the stack | |
88 \item for every parameter passed via a register, space is reserved in the stack parameter area (in order to spill the parameters if | |
89 needed - e.g. varargs) | |
331 | 90 \item ellipsis calls take floating point values in int and float registers (single precision floats are promoted to double precision as |
91 required by ellipsis calls) | |
0 | 92 \item all nonvector parameters are aligned on 4-byte boundaries |
93 \item vector parameters are aligned on 16-byte boundaries | |
94 \item composite parameters with size of 1 or 2 bytes occupy low-order bytes of their 4-byte area. INCONSISTENT with other 32-bit PPC | |
331 | 95 binary interfaces. In AIX and mac OS 9, padding bytes always follow the data structure |
0 | 96 \item composite parameters 3 bytes or larger in size occupy high-order bytes |
125 | 97 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy higher-address bytes) in their 4-byte slot on the stack, requiring extra-care for big-endian targets |
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98 \item aggregates (struct, union) with only one (non-aggregate / non-array) field are passed as if the field itself would be passed |
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99 \item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate |
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100 \item all other aggregates are passed as a sequence of words (like integer parameters) |
0 | 101 \end{itemize} |
102 | |
103 | |
104 \paragraph{Return values} | |
105 | |
106 \begin{itemize} | |
107 \item return values of integer \textless=\ 32bit or pointer type use gpr3 | |
108 \item 64 bit integers use gpr3 and gpr4 (hiword in gpr3, loword in gpr4) | |
109 \item floating point values are returned via fpr1 | |
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110 \item for all aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param |
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111 (meaning in gpr3), and callee writes return value to this space; the ptr to the aggregate is returned in gpr3 |
0 | 112 \end{itemize} |
113 | |
114 | |
115 \paragraph{Stack layout} | |
116 | |
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117 % verified/amended: TP nov 2019 (see also doc/disas_examples/ppc.darwin.disas) |
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118 Stack frame is always 16-byte aligned. Prolog opens frame with additional, fixed space for a linkage area, to hold a number of values (not all of them are required to be saved, though). Stack directly after function prolog:\\ |
0 | 119 |
120 \begin{figure}[h] | |
121 \begin{tabular}{5|3|1 1} | |
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122 & \vdots & & \\ |
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123 \hhline{~=~~} |
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124 register save area & \hspace{4cm} & & \mrrbrace{14}{caller's frame} \\ |
0 | 125 \hhline{~-~~} |
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126 local data & & & \\ |
0 | 127 \hhline{~-~~} |
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128 \mrlbrace{6}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\ |
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129 & \ldots & & \\ |
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130 & 9th word of arg data & & \\ |
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131 & gpr10 & \mrrbrace{3}{spill area (as needed)} & \\ |
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132 & \ldots & & \\ |
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133 & gpr3 & & \\ |
0 | 134 \hhline{~-~~} |
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135 \mrlbrace{6}{linkage area} & reserved & & \\ |
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136 & reserved & & \\ |
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137 & reserved & & \\ |
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138 & return address (callee saved) & & \\ |
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139 & condition reg (callee saved) & & \\ |
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140 & parent stack frame pointer & & \\ |
0 | 141 \hhline{~=~~} |
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142 register save area & & & \mrrbrace{4}{current frame} \\ |
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143 \hhline{~-~~} |
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144 local data & & & \\ |
0 | 145 \hhline{~-~~} |
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146 parameter area & & & \\ |
0 | 147 \hhline{~-~~} |
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148 linkage area & \vdots & & \\ |
0 | 149 \end{tabular} |
150 \caption{Stack layout on ppc32 Darwin} | |
151 \end{figure} | |
152 | |
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153 |
467 | 154 \clearpage |
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155 |
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156 |
0 | 157 \subsubsection{System V PPC 32-bit} |
158 | |
159 \paragraph{Status} | |
160 | |
161 \paragraph{Registers and register usage} | |
162 | |
163 \begin{table}[h] | |
77 | 164 \begin{tabular*}{0.95\textwidth}{3 B} |
76 | 165 Name & Brief description\\ |
0 | 166 \hline |
167 {\bf r0} & scratch\\ | |
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168 {\bf r1} & stack pointer, preserve\\ |
0 | 169 {\bf r2} & system-reserved\\ |
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170 {\bf r3-r4} & parameter passing and return value, scratch\\ |
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171 {\bf r5-r10} & parameter passing, scratch\\ |
0 | 172 {\bf r11-r12} & scratch\\ |
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173 {\bf r13} & small data area pointer register\\ |
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174 {\bf r14-r30} & local variables, preserve\\ |
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175 {\bf r31} & used for local variables or \emph{environment pointer}, preserve\\ |
0 | 176 {\bf f0} & scratch\\ |
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177 {\bf f1} & parameter passing and return value, scratch\\ |
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178 {\bf f2-f8} & parameter passing, scratch\\ |
0 | 179 {\bf f9-13} & scratch\\ |
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180 {\bf f14-f31} & local variables, preserve\\ |
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181 {\bf cr0-cr7} & conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\ |
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182 {\bf lr} & link register, scratch\\ |
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183 {\bf ctr} & count register, scratch \\ |
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184 {\bf xer} & fixed-point exception register, scratch\\ |
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185 {\bf fpscr} & floating-point Status and Control Register\\ |
0 | 186 % {\bf v0-v1} & scratch\\ |
187 % {\bf v2-v13} & vector parameters\\ | |
188 % {\bf v14-v19} & scratch\\ | |
189 % {\bf v20-v31} & permanent\\ | |
190 % {\bf lr} & scratch, link-register\\ | |
191 % {\bf ctr} & scratch, count-register\\ | |
192 % {\bf cr0-cr1} & scratch\\ | |
193 % {\bf cr2-cr4} & permanent\\ | |
194 % {\bf cr5-cr7} & scratch\\ | |
76 | 195 \end{tabular*} |
0 | 196 \caption{Register usage on System V ABI PowerPC Processor} |
197 \end{table} | |
198 | |
199 \paragraph{Parameter passing} | |
200 | |
201 \begin{itemize} | |
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202 \item Stack pointer (r1) is always 16-byte aligned. The EABI differs here - it is 8-byte alignment |
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203 \item 8 general-purpose registers (r3-r10) for integer and pointer types |
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204 \item 8 floating-pointer registers (f1-f8) for float (promoted to double) and double types |
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205 \item Additional arguments are passed on the stack directly after the back-chain and saved return address (8 bytes structure) on the callers stack frame |
0 | 206 \item 64-bit integer data types are passed in general-purpose registers as a whole in two |
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207 32-bit general purpose registers (an odd and an even e.g. r3 and r4), skipping an even integer register |
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208 or passed on the stack; they are never splitted into a register and stack part |
361 | 209 \item Ellipsis calls set CR bit 6 |
123 | 210 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy high-order bytes) in their 4-byte area, requiring extra-care for big-endian targets |
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211 \item no spill area is used on stack, iterating over varargs requires a specific va\_list implementation |
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212 \item aggregates (struct, union) and types \textgreater\ 64 bits are passed indirectly, as a pointer to the data (or a copy of it, if necessary to avoid modification) |
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213 \item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate |
0 | 214 \end{itemize} |
215 | |
216 \paragraph{Return values} | |
217 | |
218 \begin{itemize} | |
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219 \item 32-bit integers use register r3, 64-bit use registers r3 and r4 (hiword in r3, loword in r4) |
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220 \item floating-point values are returned using register f1 |
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221 \item for {\it non-trivial} C++ aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param |
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222 (meaning in gpr3), and callee writes return value to this space; the ptr to the aggregate is returned in gpr3 |
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223 \item aggregates (struct, union) \textless=\ 64 bits use gpr3 and gpr4 |
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224 \item for all other aggregates and types \textgreater\ 64 bits, a secret first parameter with an address to a caller allocated space is passed to the function (in gpr3), which is written to by the callee |
0 | 225 \end{itemize} |
226 | |
227 | |
228 \paragraph{Stack layout} | |
229 | |
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230 % verified/amended: TP nov 2019 (see also doc/disas_examples/ppc.sysv.disas) |
0 | 231 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\ |
232 | |
233 \begin{figure}[h] | |
234 \begin{tabular}{5|3|1 1} | |
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235 & \vdots & & \\ |
0 | 236 \hhline{~=~~} |
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237 register save area & \hspace{4cm} & & \mrrbrace{7}{caller's frame} \\ |
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239 local data & & & \\ |
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241 \mrlbrace{3}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\ |
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242 & \ldots & & \\ |
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243 & first arg passed via stack & & \\ |
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245 & return address (callee saved) & & \\ |
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246 \hhline{~-~~} |
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247 & parent stack frame pointer & & \\ |
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249 register save area & & & \mrrbrace{4}{current frame} \\ |
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251 local data & & & \\ |
0 | 252 \hhline{~-~~} |
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253 parameter area & & & \\ |
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254 \hhline{~-~~} |
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255 & \vdots & & \\ |
0 | 256 \end{tabular} |
257 \caption{Stack layout on System V ABI for PowerPC 32-bit calling convention} | |
258 \end{figure} | |
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259 |
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260 |
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261 \subsubsection{System V PPC 32-bit / Linux Standard Base version} |
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262 |
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263 This is in essence the same as the System V PPC 32-bit calling convention, but differs for aggregate return values: |
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264 % @@@AGGR could be more verbose |
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265 |
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266 \begin{itemize} |
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267 \item for all aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param |
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268 (meaning in gpr3), and callee writes return value to this space; the ptr to the aggregate is returned in gpr3 |
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269 \end{itemize} |
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270 |
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271 |
467 | 272 \clearpage |
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273 |
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274 \subsubsection{System V syscalls} |
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275 |
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276 \paragraph{Parameter passing} |
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277 |
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278 \begin{itemize} |
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279 \item syscall is issued via the {\em sc} instruction |
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280 \item kernel destroys registers r13 |
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281 \item syscall number is set in r0 |
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282 \item params are passed in registers r3 through r10 |
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283 \item no stack in use, meaning syscalls are in theory limited to eight arguments |
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284 \item register r3 holds the return value, overflow flag in conditional register cr0 signals errors in syscall |
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285 \end{itemize} |
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286 |