Mercurial > pub > dyncall > dyncall
annotate doc/manual/callconvs/callconv_ppc32.tex @ 328:276eb8c87aa0
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author | Tassilo Philipp |
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date | Fri, 22 Nov 2019 23:11:56 +0100 |
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0 | 1 %////////////////////////////////////////////////////////////////////////////// |
2 % | |
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3 % Copyright (c) 2007-2019 Daniel Adler <dadler@uni-goettingen.de>, |
0 | 4 % Tassilo Philipp <tphilipp@potion-studios.com> |
5 % | |
6 % Permission to use, copy, modify, and distribute this software for any | |
7 % purpose with or without fee is hereby granted, provided that the above | |
8 % copyright notice and this permission notice appear in all copies. | |
9 % | |
10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
17 % | |
18 %////////////////////////////////////////////////////////////////////////////// | |
19 | |
20 % ================================================== | |
21 % PowerPC 32 | |
22 % ================================================== | |
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23 \subsection{PowerPC (32bit) Calling Conventions} |
0 | 24 |
25 \paragraph{Overview} | |
26 | |
27 \begin{itemize} | |
28 \item Word size is 32 bits | |
29 \item Big endian (MSB) and litte endian (LSB) operating modes. | |
30 \item Processor operates on floats in double precision floating point arithmetc (IEEE-754) values directly (single precision is converted on the fly) | |
31 \item Apple Mac OS X/Darwin PPC is specified in "Mac OS X ABI Function Call Guide"\cite{ppcMacOSX}. It uses Big Endian (MSB). | |
32 \item Linux PPC 32-bit ABI is specified in "LSB for PPC"\cite{ppc32LSB} which is based on "System V ABI". It uses Big Endian (MSB). | |
33 \item PowerPC EABI is defined in the "PowerPC Embedded Application Binary Interface 32-Bit Implementation". | |
34 \end{itemize} | |
35 | |
36 \paragraph{\product{dyncall} support} | |
37 | |
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38 \product{Dyncall} and \product{dyncallback} are supported for PowerPC (32bit) Big Endian (MSB), for Darwin's and System V's calling convention. |
0 | 39 |
40 | |
41 \subsubsection{Mac OS X/Darwin} | |
42 | |
43 \paragraph{Registers and register usage} | |
44 | |
45 \begin{table}[h] | |
77 | 46 \begin{tabular*}{0.95\textwidth}{3 B} |
0 | 47 Name & Brief description\\ |
48 \hline | |
49 {\bf gpr0} & scratch\\ | |
50 {\bf gpr1} & stack pointer\\ | |
51 {\bf gpr2} & scratch\\ | |
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52 {\bf gpr3,gpr4} & return value, parameter 0 and 1 for integer or pointer, scratch\\ |
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53 {\bf gpr5-gpr10} & parameter 2-7 for integer or pointer parameters, scratch\\ |
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54 {\bf gpr11} & preserve\\ |
0 | 55 {\bf gpr12} & branch target for dynamic code generation\\ |
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56 {\bf gpr13-31} & preserve\\ |
0 | 57 {\bf fpr0} & scratch\\ |
238 | 58 {\bf fpr1} & floating point return value, floating point parameter 0 (always double precision)\\ |
59 {\bf fpr2-fpr13} & floating point parameters 1-12 (always double precision)\\ | |
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60 {\bf fpr14-fpr31} & preserve\\ |
0 | 61 {\bf v0-v1} & scratch\\ |
62 {\bf v2-v13} & vector parameters\\ | |
63 {\bf v14-v19} & scratch\\ | |
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64 {\bf v20-v31} & preserve\\ |
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65 {\bf lr} & link-register, scratch\\ |
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66 {\bf ctr} & count-register, scratch\\ |
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67 {\bf cr0-cr7} & conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\ |
76 | 68 \end{tabular*} |
0 | 69 \caption{Register usage on Darwin PowerPC 32-Bit} |
70 \end{table} | |
71 | |
72 \paragraph{Parameter passing} | |
73 | |
74 \begin{itemize} | |
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75 \item stack grows down |
238 | 76 \item stack parameter order: right-to-left |
77 \item caller cleans up the stack | |
0 | 78 \item the first 8 integer parameters are passed in registers gpr3-gpr10 |
79 \item the first 12 floating point parameters are passed in registers fpr1-fpr13 | |
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80 \item 64 bit arguments are passed as if they were two 32 bit arguments, without skipping registers for alignment (this means passing half via a register and half via the stack is allowed) |
0 | 81 \item if a float parameter is passed via a register, gpr registers are skipped for subsequent integer parameters (based on the size of |
82 the float - 1 register for single precision and 2 for double precision floating point values) | |
83 \item the caller pushes subsequent parameters onto the stack | |
84 \item for every parameter passed via a register, space is reserved in the stack parameter area (in order to spill the parameters if | |
85 needed - e.g. varargs) | |
86 \item ellipsis calls take floating point values in int and float registers (single precision floats are promoted to double precision | |
87 as defined for ellipsis calls) | |
88 \item all nonvector parameters are aligned on 4-byte boundaries | |
89 \item vector parameters are aligned on 16-byte boundaries | |
90 \item composite parameters with size of 1 or 2 bytes occupy low-order bytes of their 4-byte area. INCONSISTENT with other 32-bit PPC | |
91 binary interfaces. In AIX and OS 9, padding bytes always follow the data structure | |
92 \item composite parameters 3 bytes or larger in size occupy high-order bytes | |
125 | 93 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy higher-address bytes) in their 4-byte slot on the stack, requiring extra-care for big-endian targets |
0 | 94 \end{itemize} |
95 | |
96 | |
97 \paragraph{Return values} | |
98 | |
99 \begin{itemize} | |
100 \item return values of integer \textless=\ 32bit or pointer type use gpr3 | |
101 \item 64 bit integers use gpr3 and gpr4 (hiword in gpr3, loword in gpr4) | |
102 \item floating point values are returned via fpr1 | |
103 \item structures \textless=\ 64 bits use gpr3 and gpr4 | |
104 \item for types \textgreater\ 64 bits, a secret first parameter with an address to the return value is passed | |
105 \end{itemize} | |
106 | |
107 | |
108 \paragraph{Stack layout} | |
109 | |
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110 % verified/amended: TP nov 2019 (see also doc/disas_examples/ppc.darwin.disas) |
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111 Stack frame is always 16-byte aligned. Prolog opens frame with additional, fixed space for a linkage area, to hold a number of values (not all of them are required to be saved, though). Stack directly after function prolog:\\ |
0 | 112 |
113 \begin{figure}[h] | |
114 \begin{tabular}{5|3|1 1} | |
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115 & \vdots & & \\ |
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116 \hhline{~=~~} |
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117 register save area & \hspace{4cm} & & \mrrbrace{14}{caller's frame} \\ |
0 | 118 \hhline{~-~~} |
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119 local data & & & \\ |
0 | 120 \hhline{~-~~} |
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121 \mrlbrace{6}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\ |
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122 & \ldots & & \\ |
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123 & 9th word of arg data & & \\ |
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124 & gpr10 & \mrrbrace{3}{spill area (as needed)} & \\ |
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125 & \ldots & & \\ |
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126 & gpr3 & & \\ |
0 | 127 \hhline{~-~~} |
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128 \mrlbrace{6}{linkage area} & reserved & & \\ |
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129 & reserved & & \\ |
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130 & reserved & & \\ |
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131 & return address (callee saved) & & \\ |
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132 & condition reg (callee saved) & & \\ |
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133 & parent stack frame pointer & & \\ |
0 | 134 \hhline{~=~~} |
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135 register save area & & & \mrrbrace{4}{current frame} \\ |
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136 \hhline{~-~~} |
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137 local data & & & \\ |
0 | 138 \hhline{~-~~} |
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139 parameter area & & & \\ |
0 | 140 \hhline{~-~~} |
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141 linkage area & \vdots & & \\ |
0 | 142 \end{tabular} |
143 \caption{Stack layout on ppc32 Darwin} | |
144 \end{figure} | |
145 | |
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146 |
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147 \newpage |
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148 |
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149 |
0 | 150 \subsubsection{System V PPC 32-bit} |
151 | |
152 \paragraph{Status} | |
153 | |
154 \paragraph{Registers and register usage} | |
155 | |
156 \begin{table}[h] | |
77 | 157 \begin{tabular*}{0.95\textwidth}{3 B} |
76 | 158 Name & Brief description\\ |
0 | 159 \hline |
160 {\bf r0} & scratch\\ | |
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161 {\bf r1} & stack pointer, preserve\\ |
0 | 162 {\bf r2} & system-reserved\\ |
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163 {\bf r3-r4} & parameter passing and return value, scratch\\ |
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164 {\bf r5-r10} & parameter passing, scratch\\ |
0 | 165 {\bf r11-r12} & scratch\\ |
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166 {\bf r13} & small data area pointer register\\ |
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167 {\bf r14-r30} & local variables, preserve\\ |
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168 {\bf r31} & used for local variables or \emph{environment pointer}, preserve\\ |
0 | 169 {\bf f0} & scratch\\ |
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170 {\bf f1} & parameter passing and return value, scratch\\ |
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171 {\bf f2-f8} & parameter passing, scratch\\ |
0 | 172 {\bf f9-13} & scratch\\ |
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173 {\bf f14-f31} & local variables, preserve\\ |
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174 {\bf cr0-cr7} & conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\ |
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175 {\bf lr} & link register, scratch\\ |
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176 {\bf ctr} & count register, scratch \\ |
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177 {\bf xer} & fixed-point exception register, scratch\\ |
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178 {\bf fpscr} & floating-point Status and Control Register\\ |
0 | 179 % {\bf v0-v1} & scratch\\ |
180 % {\bf v2-v13} & vector parameters\\ | |
181 % {\bf v14-v19} & scratch\\ | |
182 % {\bf v20-v31} & permanent\\ | |
183 % {\bf lr} & scratch, link-register\\ | |
184 % {\bf ctr} & scratch, count-register\\ | |
185 % {\bf cr0-cr1} & scratch\\ | |
186 % {\bf cr2-cr4} & permanent\\ | |
187 % {\bf cr5-cr7} & scratch\\ | |
76 | 188 \end{tabular*} |
0 | 189 \caption{Register usage on System V ABI PowerPC Processor} |
190 \end{table} | |
191 | |
192 \paragraph{Parameter passing} | |
193 | |
194 \begin{itemize} | |
195 \item Stack pointer (r1) is always 16-byte aligned. The EABI differs here - it is 8-byte alignment. | |
196 \item 8 general-purpose registers (r3-r10) for integer and pointer types. | |
197 \item 8 floating-pointer registers (f1-f8) for float (promoted to double) and double types. | |
198 \item Additional arguments are passed on the stack directly after the back-chain and saved return address (8 bytes structure) on the callers stack frame. | |
199 \item 64-bit integer data types are passed in general-purpose registers as a whole in two | |
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200 32-bit general purpose registers (an odd and an even e.g. r3 and r4), skipping an even integer register |
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201 or passed on the stack; they are never splitted into a register and stack part |
0 | 202 \item Ellipse calls set CR bit 6 |
123 | 203 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy high-order bytes) in their 4-byte area, requiring extra-care for big-endian targets |
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204 \item no spill area is used on stack, iterating over varargs requires a specific va\_list implementation |
0 | 205 \end{itemize} |
206 | |
207 \paragraph{Return values} | |
208 | |
209 \begin{itemize} | |
210 \item 32-bit integers use register r3, 64-bit use registers r3 and r4 (hiword in r3, loword in r4). | |
211 \item floating-point values are returned using register f1. | |
212 \end{itemize} | |
213 | |
214 | |
215 \paragraph{Stack layout} | |
216 | |
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217 % verified/amended: TP nov 2019 (see also doc/disas_examples/ppc.sysv.disas) |
0 | 218 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\ |
219 | |
220 \begin{figure}[h] | |
221 \begin{tabular}{5|3|1 1} | |
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222 & \vdots & & \\ |
0 | 223 \hhline{~=~~} |
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224 register save area & \hspace{4cm} & & \mrrbrace{7}{caller's frame} \\ |
0 | 225 \hhline{~-~~} |
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226 local data & & & \\ |
0 | 227 \hhline{~-~~} |
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228 \mrlbrace{3}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\ |
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229 & \ldots & & \\ |
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230 & first arg passed via stack & & \\ |
0 | 231 \hhline{~-~~} |
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232 & return address (callee saved) & & \\ |
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233 \hhline{~-~~} |
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234 & parent stack frame pointer & & \\ |
0 | 235 \hhline{~=~~} |
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236 register save area & & & \mrrbrace{4}{current frame} \\ |
0 | 237 \hhline{~-~~} |
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238 local data & & & \\ |
0 | 239 \hhline{~-~~} |
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240 parameter area & & & \\ |
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241 \hhline{~-~~} |
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242 & \vdots & & \\ |
0 | 243 \end{tabular} |
244 \caption{Stack layout on System V ABI for PowerPC 32-bit calling convention} | |
245 \end{figure} | |
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246 |