annotate doc/manual/callconvs/callconv_ppc32.tex @ 238:05181c5a6edd

- ppc32 doc tweak
author Tassilo Philipp
date Tue, 02 May 2017 03:00:55 +0200
parents f1fc1c836baf
children cde7b1f3b8f2
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
1 %//////////////////////////////////////////////////////////////////////////////
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
2 %
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
3 % Copyright (c) 2007,2009 Daniel Adler <dadler@uni-goettingen.de>,
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
4 % Tassilo Philipp <tphilipp@potion-studios.com>
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
5 %
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
6 % Permission to use, copy, modify, and distribute this software for any
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
7 % purpose with or without fee is hereby granted, provided that the above
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
8 % copyright notice and this permission notice appear in all copies.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
9 %
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
17 %
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
18 %//////////////////////////////////////////////////////////////////////////////
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
19
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
20 % ==================================================
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
21 % PowerPC 32
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
22 % ==================================================
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
23 \subsection{PowerPC (32bit) Calling Convention}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
24
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
25 \paragraph{Overview}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
26
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
27 \begin{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
28 \item Word size is 32 bits
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
29 \item Big endian (MSB) and litte endian (LSB) operating modes.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
30 \item Processor operates on floats in double precision floating point arithmetc (IEEE-754) values directly (single precision is converted on the fly)
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
31 \item Apple Mac OS X/Darwin PPC is specified in "Mac OS X ABI Function Call Guide"\cite{ppcMacOSX}. It uses Big Endian (MSB).
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
32 \item Linux PPC 32-bit ABI is specified in "LSB for PPC"\cite{ppc32LSB} which is based on "System V ABI". It uses Big Endian (MSB).
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
33 \item PowerPC EABI is defined in the "PowerPC Embedded Application Binary Interface 32-Bit Implementation".
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
34 \end{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
35
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
36 \paragraph{\product{dyncall} support}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
37
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
38 \product{Dyncall} and \product{dyncallback} are supported for PowerPC (32bit) Big Endian (MSB) on Darwin (tested on Apple Mac OS X) and Linux, however, fail for *BSD.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
39
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
40
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
41 \subsubsection{Mac OS X/Darwin}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
42
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
43 \paragraph{Registers and register usage}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
44
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
45 \begin{table}[h]
77
e441ef3ec782 - manual layout tweaks
cslag
parents: 76
diff changeset
46 \begin{tabular*}{0.95\textwidth}{3 B}
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
47 Name & Brief description\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
48 \hline
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
49 {\bf gpr0} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
50 {\bf gpr1} & stack pointer\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
51 {\bf gpr2} & scratch\\
238
05181c5a6edd - ppc32 doc tweak
Tassilo Philipp
parents: 125
diff changeset
52 {\bf gpr3,gpr4} & return value, parameter 0 and 1 for integer or pointer\\
05181c5a6edd - ppc32 doc tweak
Tassilo Philipp
parents: 125
diff changeset
53 {\bf gpr5-gpr10} & parameter 2-7 for integer or pointer parameters\\
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
54 {\bf gpr11} & permanent\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
55 {\bf gpr12} & branch target for dynamic code generation\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
56 {\bf gpr13-31} & permanent\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
57 {\bf fpr0} & scratch\\
238
05181c5a6edd - ppc32 doc tweak
Tassilo Philipp
parents: 125
diff changeset
58 {\bf fpr1} & floating point return value, floating point parameter 0 (always double precision)\\
05181c5a6edd - ppc32 doc tweak
Tassilo Philipp
parents: 125
diff changeset
59 {\bf fpr2-fpr13} & floating point parameters 1-12 (always double precision)\\
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
60 {\bf fpr14-fpr31} & permanent\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
61 {\bf v0-v1} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
62 {\bf v2-v13} & vector parameters\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
63 {\bf v14-v19} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
64 {\bf v20-v31} & permanent\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
65 {\bf lr} & scratch, link-register\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
66 {\bf ctr} & scratch, count-register\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
67 {\bf cr0-cr1} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
68 {\bf cr2-cr4} & permanent\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
69 {\bf cr5-cr7} & scratch\\
76
7ca46969e0ad - tweaks in manual, mainly for html generation
cslag
parents: 0
diff changeset
70 \end{tabular*}
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
71 \caption{Register usage on Darwin PowerPC 32-Bit}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
72 \end{table}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
73
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
74 \paragraph{Parameter passing}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
75
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
76 \begin{itemize}
238
05181c5a6edd - ppc32 doc tweak
Tassilo Philipp
parents: 125
diff changeset
77 \item stack parameter order: right-to-left
05181c5a6edd - ppc32 doc tweak
Tassilo Philipp
parents: 125
diff changeset
78 \item caller cleans up the stack
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
79 \item the first 8 integer parameters are passed in registers gpr3-gpr10
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
80 \item the first 12 floating point parameters are passed in registers fpr1-fpr13
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
81 \item if a float parameter is passed via a register, gpr registers are skipped for subsequent integer parameters (based on the size of
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
82 the float - 1 register for single precision and 2 for double precision floating point values)
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
83 \item the caller pushes subsequent parameters onto the stack
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
84 \item for every parameter passed via a register, space is reserved in the stack parameter area (in order to spill the parameters if
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
85 needed - e.g. varargs)
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
86 \item ellipsis calls take floating point values in int and float registers (single precision floats are promoted to double precision
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
87 as defined for ellipsis calls)
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
88 \item all nonvector parameters are aligned on 4-byte boundaries
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
89 \item vector parameters are aligned on 16-byte boundaries
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
90 \item composite parameters with size of 1 or 2 bytes occupy low-order bytes of their 4-byte area. INCONSISTENT with other 32-bit PPC
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
91 binary interfaces. In AIX and OS 9, padding bytes always follow the data structure
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
92 \item composite parameters 3 bytes or larger in size occupy high-order bytes
125
f1fc1c836baf - mips doc stuff
cslag
parents: 123
diff changeset
93 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy higher-address bytes) in their 4-byte slot on the stack, requiring extra-care for big-endian targets
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
94 \end{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
95
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
96
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
97 \paragraph{Return values}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
98
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
99 \begin{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
100 \item return values of integer \textless=\ 32bit or pointer type use gpr3
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
101 \item 64 bit integers use gpr3 and gpr4 (hiword in gpr3, loword in gpr4)
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
102 \item floating point values are returned via fpr1
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
103 \item structures \textless=\ 64 bits use gpr3 and gpr4
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
104 \item for types \textgreater\ 64 bits, a secret first parameter with an address to the return value is passed
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
105 \end{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
106
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
107 \pagebreak
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
108
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
109 \paragraph{Stack layout}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
110
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
111 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
112
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
113 \begin{figure}[h]
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
114 \begin{tabular}{5|3|1 1}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
115 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
116 & \vdots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
117 \hhline{~=~~}
92
5c3fa8897e0e - manual work
cslag
parents: 90
diff changeset
118 local data & \hspace{4cm} & & \mrrbrace{13}{caller's frame} \\
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
119 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
120 \mrlbrace{6}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
121 & \ldots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
122 & \ldots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
123 & \ldots & \mrrbrace{3}{spill area (as needed)} & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
124 & \ldots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
125 & gpr3 or fpr1 & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
126 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
127 \mrlbrace{6}{linkage area} & reserved & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
128 & reserved & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
129 & reserved & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
130 & return address & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
131 & reserved for callee & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
132 & saved by callee & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
133 \hhline{~=~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
134 local data & & & \mrrbrace{3}{current frame} \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
135 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
136 parameter area & & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
137 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
138 linkage area & \vdots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
139 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
140 \end{tabular}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
141 \caption{Stack layout on ppc32 Darwin}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
142 \end{figure}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
143
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
144 \subsubsection{System V PPC 32-bit}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
145
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
146 \paragraph{Status}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
147
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
148 \begin{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
149 \item C++ this calls do not work.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
150 \item Callbacks don't work on *BSD.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
151 \end{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
152
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
153 \paragraph{Registers and register usage}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
154
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
155 \begin{table}[h]
77
e441ef3ec782 - manual layout tweaks
cslag
parents: 76
diff changeset
156 \begin{tabular*}{0.95\textwidth}{3 B}
76
7ca46969e0ad - tweaks in manual, mainly for html generation
cslag
parents: 0
diff changeset
157 Name & Brief description\\
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
158 \hline
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
159 {\bf r0} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
160 {\bf r1} & stack pointer\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
161 {\bf r2} & system-reserved\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
162 {\bf r3-r4} & parameter passing and return value\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
163 {\bf r5-r10} & parameter passing\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
164 {\bf r11-r12} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
165 {\bf r13} & Small data area pointer register\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
166 {\bf r14-r30} & Local variables\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
167 {\bf r31} & Used for local variables or \emph{environment pointer}\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
168 {\bf f0} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
169 {\bf f1} & parameter passing and return value\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
170 {\bf f2-f8} & parameter passing\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
171 {\bf f9-13} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
172 {\bf f14-f31} & Local variables\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
173 {\bf cr0-cr7} & Conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
174 {\bf lr} & Link register (scratch)\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
175 {\bf ctr} & Count register (scratch) \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
176 {\bf xer} & Fixed-point exception register (scratch)\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
177 {\bf fpscr} & Floating-point Status and Control Register\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
178 % {\bf v0-v1} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
179 % {\bf v2-v13} & vector parameters\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
180 % {\bf v14-v19} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
181 % {\bf v20-v31} & permanent\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
182 % {\bf lr} & scratch, link-register\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
183 % {\bf ctr} & scratch, count-register\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
184 % {\bf cr0-cr1} & scratch\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
185 % {\bf cr2-cr4} & permanent\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
186 % {\bf cr5-cr7} & scratch\\
76
7ca46969e0ad - tweaks in manual, mainly for html generation
cslag
parents: 0
diff changeset
187 \end{tabular*}
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
188 \caption{Register usage on System V ABI PowerPC Processor}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
189 \end{table}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
190
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
191 \paragraph{Parameter passing}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
192
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
193 \begin{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
194 \item Stack pointer (r1) is always 16-byte aligned. The EABI differs here - it is 8-byte alignment.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
195 \item 8 general-purpose registers (r3-r10) for integer and pointer types.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
196 \item 8 floating-pointer registers (f1-f8) for float (promoted to double) and double types.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
197 \item Additional arguments are passed on the stack directly after the back-chain and saved return address (8 bytes structure) on the callers stack frame.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
198 \item 64-bit integer data types are passed in general-purpose registers as a whole in two
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
199 32-bit general purpose registers (an odd and an even e.g. r3 and r4), probably skipping an even integer register.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
200 or passed on the stack. They are never splitted into a register and stack part.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
201 \item Ellipse calls set CR bit 6
123
d203ba52c246 - manual callconv clarifications
cslag
parents: 95
diff changeset
202 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy high-order bytes) in their 4-byte area, requiring extra-care for big-endian targets
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
203 \end{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
204
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
205 \paragraph{Return values}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
206
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
207 \begin{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
208 \item 32-bit integers use register r3, 64-bit use registers r3 and r4 (hiword in r3, loword in r4).
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
209 \item floating-point values are returned using register f1.
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
210 \end{itemize}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
211
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
212 \pagebreak
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
213
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
214 \paragraph{Stack layout}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
215
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
216 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
217
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
218 \begin{figure}[h]
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
219 \begin{tabular}{5|3|1 1}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
220 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
221 & \vdots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
222 \hhline{~=~~}
92
5c3fa8897e0e - manual work
cslag
parents: 90
diff changeset
223 local data & \hspace{4cm} & & \mrrbrace{6}{caller's frame} \\
0
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
224 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
225 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
226 & \ldots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
227 & \ldots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
228 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
229 & saved return address (for callee) & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
230 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
231 & parent stack frame pointer & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
232 \hhline{~=~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
233 local data & & & \mrrbrace{3}{current frame} \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
234 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
235 parameter area & & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
236 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
237 & \vdots & & \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
238 \hhline{~-~~}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
239 \end{tabular}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
240 \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
241 \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
242 \\
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
243 \caption{Stack layout on System V ABI for PowerPC 32-bit calling convention}
3e629dc19168 initial from svn dyncall-1745
Daniel Adler
parents:
diff changeset
244 \end{figure}