Mercurial > pub > dyncall > dyncall
annotate doc/manual/callconvs/callconv_mips32.tex @ 304:6869d834a847
- mips32 doc
| author | Tassilo Philipp |
|---|---|
| date | Wed, 23 May 2018 11:39:40 +0200 |
| parents | d55f9d508074 |
| children | b104c5beec8b |
| rev | line source |
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| 0 | 1 %////////////////////////////////////////////////////////////////////////////// |
| 2 % | |
| 3 % Copyright (c) 2007,2009 Daniel Adler <dadler@uni-goettingen.de>, | |
| 4 % Tassilo Philipp <tphilipp@potion-studios.com> | |
| 5 % | |
| 6 % Permission to use, copy, modify, and distribute this software for any | |
| 7 % purpose with or without fee is hereby granted, provided that the above | |
| 8 % copyright notice and this permission notice appear in all copies. | |
| 9 % | |
| 10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| 11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| 12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| 13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| 14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| 15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| 16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| 17 % | |
| 18 %////////////////////////////////////////////////////////////////////////////// | |
| 19 | |
| 117 | 20 \subsection{MIPS32 Calling Convention} |
| 0 | 21 |
| 22 \paragraph{Overview} | |
| 23 | |
| 24 Multiple revisions of the MIPS Instruction set exist, namely MIPS I, MIPS II, MIPS III, MIPS IV, MIPS32 and MIPS64. | |
| 117 | 25 Nowadays, MIPS32 and MIPS64 are the main ones used for 32-bit and 64-bit instruction sets, respectively.\\ |
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26 Given MIPS processors are often used for embedded devices, several add-on extensions exist for the MIPS family, for example: |
| 0 | 27 |
| 28 \begin{description} | |
| 29 \item [MIPS-3D] simple floating-point SIMD instructions dedicated to common 3D tasks. | |
| 30 \item [MDMX] (MaDMaX) more extensive integer SIMD instruction set using 64 bit floating-point registers. | |
| 31 \item [MIPS16e] adds compression to the instruction stream to make programs take up less room (allegedly a response to the THUMB instruction set of the ARM architecture). | |
| 32 \item [MIPS MT] multithreading additions to the system similar to HyperThreading. | |
| 33 \end{description} | |
| 34 | |
| 117 | 35 Unfortunately, there is actually no such thing as "The MIPS Calling Convention". Many possible conventions are used |
| 36 by many different environments such as \emph{O32}\cite{MIPSo32}, \emph{O64}\cite{MIPSo64}, \emph{N32}\cite{MIPSn32/n64}, \emph{N64}\cite{MIPSn32/n64}, \emph{EABI}\cite{MIPSeabi} and \emph{NUBI}\cite{MIPSnubi}.\\ | |
| 0 | 37 |
| 38 \paragraph{\product{dyncall} support} | |
| 39 | |
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40 Currently, dyncall supports for MIPS 32-bit architectures the widely-used O32 calling convention (for all four combinations of big/little-endian, and soft/hard-float targets), |
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41 as well as EABI (little-endian/hard-float, which is used on the Homebrew SDK for the Playstation Portable). \product{dyncall} currently does not support MIPS16e |
| 139 | 42 (contrary to the like-minded ARM-THUMB, which is supported). Both, calls and callbacks are supported. |
| 0 | 43 |
| 44 \subsubsection{MIPS EABI 32-bit Calling Convention} | |
| 45 | |
| 46 \paragraph{Register usage} | |
| 47 | |
| 48 \begin{table}[h] | |
| 77 | 49 \begin{tabular*}{0.95\textwidth}{lll} |
| 108 | 50 Name & Alias & Brief description\\ |
| 51 \hline | |
| 52 {\bf \$0} & {\bf \$zero} & Hardware zero \\ | |
| 53 {\bf \$1} & {\bf \$at} & Assembler temporary \\ | |
| 54 {\bf \$2-\$3} & {\bf \$v0-\$v1} & Integer results \\ | |
| 110 | 55 {\bf \$4-\$11} & {\bf \$a0-\$a7} & Integer arguments, or double precision float arguments\\ |
| 108 | 56 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & Integer temporaries \\ |
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57 {\bf \$25} & {\bf \$t9} & Integer temporary, holds address of called function for PIC calls (by convention) \\ |
| 108 | 58 {\bf \$16-\$23} & {\bf \$s0-\$s7} & Preserved \\ |
| 59 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & Reserved for kernel \\ | |
| 60 {\bf \$28} & {\bf \$gp} & Global pointer, preserve \\ | |
| 61 {\bf \$29} & {\bf \$sp} & Stack pointer, preserve \\ | |
| 62 {\bf \$30} & {\bf \$s8} & Frame pointer, preserve \\ | |
| 63 {\bf \$31} & {\bf \$ra} & Return address, preserve \\ | |
| 64 {\bf hi, lo} & & Multiply/divide special registers \\ | |
| 65 {\bf \$f0,\$f2} & & Float results \\ | |
| 66 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & Float temporaries \\ | |
| 117 | 67 {\bf \$f12-\$f19} & & Single precision float arguments \\ |
| 76 | 68 \end{tabular*} |
| 98 | 69 \caption{Register usage on MIPS32 EABI calling convention} |
| 0 | 70 \end{table} |
| 71 | |
| 72 \paragraph{Parameter passing} | |
| 73 | |
| 74 \begin{itemize} | |
| 98 | 75 \item Stack grows down |
| 0 | 76 \item Stack parameter order: right-to-left |
| 77 \item Caller cleans up the stack | |
| 190 | 78 \item first 8 integers (\textless=\ 32bit) are passed in registers \$a0-\$a7 |
| 110 | 79 \item first 8 single precision floating point arguments are passed in registers \$f12-\$f19 |
| 108 | 80 \item if either integer or float registers are used up, the stack is used |
| 111 | 81 \item 64-bit stack arguments are always aligned to 8 bytes |
| 110 | 82 \item 64-bit integers or double precision floats are passed on two general purpose registers starting at an even register number, skipping one odd register |
| 83 \item \$a0-\$a7 and \$f12-\$f19 are not required to be preserved | |
| 84 \item results are returned in \$v0 (32-bit), \$v0 and \$v1 (64-bit), \$f0 or \$f0 and \$f2 (2 $\times$ 32 bit float e.g. complex) | |
| 0 | 85 \end{itemize} |
| 86 | |
| 87 \paragraph{Stack layout} | |
| 88 | |
| 89 Stack directly after function prolog:\\ | |
| 90 | |
| 91 \begin{figure}[h] | |
| 92 \begin{tabular}{5|3|1 1} | |
| 93 \hhline{~-~~} | |
| 92 | 94 & \vdots & & \\ |
| 95 \hhline{~=~~} | |
| 96 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ | |
| 97 \hhline{~-~~} | |
| 117 | 98 local data & & & \\ |
| 92 | 99 \hhline{~-~~} |
| 100 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ | |
| 101 & \ldots & & \\ | |
| 102 & \ldots & & \\ | |
| 0 | 103 \hhline{~=~~} |
| 92 | 104 register save area (with return address) & & & \mrrbrace{5}{current frame} \\ |
| 0 | 105 \hhline{~-~~} |
| 92 | 106 local data & & & \\ |
| 0 | 107 \hhline{~-~~} |
| 92 | 108 parameter area & & & \\ |
| 0 | 109 \hhline{~-~~} |
| 92 | 110 & \vdots & & \\ |
| 0 | 111 \hhline{~-~~} |
| 112 \end{tabular} | |
| 113 \caption{Stack layout on mips32 eabi calling convention} | |
| 114 \end{figure} | |
| 115 | |
| 98 | 116 \newpage |
| 117 | |
| 95 | 118 \subsubsection{MIPS O32 32-bit Calling Convention} |
| 119 | |
| 98 | 120 \paragraph{Register usage} |
| 121 | |
| 122 \begin{table}[h] | |
| 123 \begin{tabular*}{0.95\textwidth}{lll} | |
| 108 | 124 Name & Alias & Brief description\\ |
| 98 | 125 \hline |
| 108 | 126 {\bf \$0} & {\bf \$zero} & hardware zero \\ |
| 127 {\bf \$1} & {\bf \$at} & assembler temporary \\ | |
| 304 | 128 {\bf \$2-\$3} & {\bf \$v0-\$v1} & return value (only integer on hard-float targets), scratch \\ |
| 129 {\bf \$4-\$7} & {\bf \$a0-\$a3} & first arguments (only integer on hard-float targets), scratch\\ | |
| 108 | 130 {\bf \$8-\$15,\$24} & {\bf \$t0-\$t7,\$t8} & temporaries, scratch \\ |
| 304 | 131 {\bf \$25} & {\bf \$t9} & temporary, holds address of called function for PIC calls (by convention) \\ |
| 108 | 132 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserved \\ |
| 133 {\bf \$26,\$27} & {\bf \$k0,\$k1} & reserved for kernel \\ | |
| 117 | 134 {\bf \$28} & {\bf \$gp} & global pointer, preserved by caller \\ |
| 108 | 135 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\ |
| 136 {\bf \$30} & {\bf \$fp} & frame pointer, preserve \\ | |
| 137 {\bf \$31} & {\bf \$ra} & return address, preserve \\ | |
| 138 {\bf hi, lo} & & multiply/divide special registers \\ | |
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139 {\bf \$f0-\$f3} & & only on hard-float targets: float return value, scratch \\ |
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140 {\bf \$f4-\$f11,\$f16-\$f19} & & only on hard-float targets: float temporaries, scratch \\ |
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141 {\bf \$f12-\$f15} & & only on hard-float targets: first floating point arguments, scratch \\ |
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142 {\bf \$f20-\$f31} & & only on hard-float targets: preserved \\ |
| 98 | 143 \end{tabular*} |
| 144 \caption{Register usage on MIPS O32 calling convention} | |
| 145 \end{table} | |
| 146 | |
| 147 \paragraph{Parameter passing} | |
| 148 | |
| 149 \begin{itemize} | |
| 150 \item Stack grows down | |
| 151 \item Stack parameter order: right-to-left | |
| 152 \item Caller cleans up the stack | |
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153 \item Caller is required to always leave a 16-byte spill area for \$a0-\$a3 at the and of {\bf its} frame, to be used and spilled to by the callee, if needed |
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154 \item The different stack areas (local data, register save area, parameter area) are each aligned to 8 bytes |
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155 \item generally, first four 32bit arguments are passed in registers \$a0-\$a3, respectively (only on hard-float targets: see below for exceptions if first arg is a float) |
| 98 | 156 \item subsequent parameters are passed vie the stack |
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157 \item 64-bit params passed via registers are passed using either two registers (starting at an even register number, skipping an odd one if necessary), or via the stack using an 8-byte alignment |
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158 \item only on hard-float targets: if the very first call argument is a float, up to 2 floats or doubles can be passed via \$f12 and \$f14, respectively, for first and second argument |
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159 \item only on hard-float targets: if any arguments are passed via float registers, skip \$a0-\$a3 for subsequent arguments as if the values were passed via them |
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160 \item only on hard-float targets: note that if the first argument is not a float, but the second, it'll get passed via the \$a? registers |
| 304 | 161 \item results are returned in \$v0 and \$v1, with \$v0 for all values < 64bit (only integer on hard-float targets) |
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162 \item only on hard-float targets: floating point results are returned in \$f0 (32-bit float), or \$f0 and \$f3 (64bit float) |
| 304 | 163 \item single precision float parameters (32 bit) are right-justified in their 8-byte slot on the stack on big endian targets, as they aren't promoted @@@ |
| 98 | 164 \end{itemize} |
| 165 | |
| 166 \paragraph{Stack layout} | |
| 167 | |
| 168 Stack directly after function prolog:\\ | |
| 169 | |
| 170 \begin{figure}[h] | |
| 171 \begin{tabular}{5|3|1 1} | |
| 172 \hhline{~-~~} | |
| 117 | 173 & \vdots & & \\ |
| 98 | 174 \hhline{~=~~} |
| 175 local data & \hspace{4cm} & & \mrrbrace{12}{caller's frame} \\ | |
| 176 \hhline{~-~~} | |
| 117 | 177 register save area & return address & & \\ |
| 178 & s7 & & \\ | |
| 179 & \vdots & & \\ | |
| 180 & s0 & & \\ | |
| 98 | 181 \hhline{~-~~} |
| 117 | 182 \mrlbrace{7}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ |
| 183 & \ldots & & \\ | |
| 184 & \ldots & & \\ | |
| 185 & a3 & \mrrbrace{4}{spill area} & \\ | |
| 186 & a2 & & \\ | |
| 187 & a1 & & \\ | |
| 188 & a0 & & \\ | |
| 98 | 189 \hhline{~=~~} |
| 117 | 190 local data & & & \mrrbrace{5}{current frame} \\ |
| 98 | 191 \hhline{~-~~} |
| 117 | 192 register save area (with return address) & & & \\ |
| 98 | 193 \hhline{~-~~} |
| 117 | 194 parameter area & & & \\ |
| 195 & \vdots & & \\ | |
| 98 | 196 \hhline{~-~~} |
| 197 \end{tabular} | |
| 198 \caption{Stack layout on MIPS O32 calling convention} | |
| 199 \end{figure} | |
| 200 | |
| 201 \newpage | |
| 95 | 202 |