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1 %//////////////////////////////////////////////////////////////////////////////
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2 %
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3 % Copyright (c) 2007,2009 Daniel Adler <dadler@uni-goettingen.de>,
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4 % Tassilo Philipp <tphilipp@potion-studios.com>
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5 %
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6 % Permission to use, copy, modify, and distribute this software for any
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7 % purpose with or without fee is hereby granted, provided that the above
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8 % copyright notice and this permission notice appear in all copies.
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9 %
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10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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17 %
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18 %//////////////////////////////////////////////////////////////////////////////
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19
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20 \subsection{MIPS Calling Convention}
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21
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22 \paragraph{Overview}
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23
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24 The MIPS family of processors is based on the MIPS processor architecture.
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25 Multiple revisions of the MIPS Instruction set exist, namely MIPS I, MIPS II, MIPS III, MIPS IV, MIPS32 and MIPS64.
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26 Today, MIPS32 and MIPS64 for 32-bit and 64-bit respectively.\\
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27 Several add-on extensions exist for the MIPS family:
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28
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29 \begin{description}
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30 \item [MIPS-3D] simple floating-point SIMD instructions dedicated to common 3D tasks.
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31 \item [MDMX] (MaDMaX) more extensive integer SIMD instruction set using 64 bit floating-point registers.
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32 \item [MIPS16e] adds compression to the instruction stream to make programs take up less room (allegedly a response to the THUMB instruction set of the ARM architecture).
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33 \item [MIPS MT] multithreading additions to the system similar to HyperThreading.
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34 \end{description}
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35
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36 Unfortunately, there is actually no such thing as "The MIPS Calling Convention". Many possible conventions are used
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37 by many different environments such as \emph{32}, \emph{O64}, \emph{N32}, \emph{64} and \emph{EABI}.
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38
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39 \paragraph{\product{dyncall} support}
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40
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41 Currently, dyncall supports the EABI calling convention which is used on the Homebrew SDK for the Playstation Portable.
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42 As documentation for this EABI is unofficial, this port is currently experimental.
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43
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44 \subsubsection{MIPS EABI 32-bit Calling Convention}
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45
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46 \paragraph{Register usage}
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47
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48 \begin{table}[h]
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49 \begin{tabular}{lll}
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50 \hline
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51 Name & Alias & Brief description\\
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52 \hline
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53 {\bf \$0} & {\bf \$zero} & Hardware zero \\
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54 {\bf \$1} & {\bf \$at} & Assembler temporary \\
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55 {\bf \$2-\$3} & {\bf \$v0-\$v1} & Integer results \\
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56 {\bf \$4-\$11} & {\bf \$a0-\$a7} & Integer arguments\\
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57 {\bf \$12-\$15,\$24,\$25} & {\bf \$t4-\$t7,\$t8,\$t9} & Integer temporaries \\
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58 {\bf \$25} & {\bf \$t9} & Integer temporary, hold the address of the called function for all PIC calls (by convention) \\
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59 {\bf \$16-\$23} & {\bf \$s0-\$s7} & Preserved \\
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60 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & Reserved for kernel \\
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61 {\bf \$28} & {\bf \$gp} & Global pointer \\
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62 {\bf \$29} & {\bf \$sp} & Stack pointer \\
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63 {\bf \$30} & {\bf \$s8} & Frame pointer \\
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64 {\bf \$31} & {\bf \$ra} & Return address \\
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65 {\bf hi, lo} & & Multiply/divide special registers \\
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66 {\bf \$f0,\$f2} & & Float results \\
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67 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & Float temporaries \\
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68 {\bf \$f12-\$f19} & & Float arguments \\
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69 \end{tabular}
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70 \caption{Register usage on mips32 eabi calling convention}
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71 \end{table}
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72
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73 \paragraph{Parameter passing}
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74
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75 \begin{itemize}
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76 \item Stack parameter order: right-to-left
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77 \item Caller cleans up the stack
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78 \item Stack always aligned to 8 bytes.
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79 \item first 8 integers and floats are passed independently in registers using \$a0-\$a7 and \$f12-\$f19, respectively.
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80 \item if either integer or float registers are consumed up, the stack is used.
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81 \item 64-bit floats and integers are passed on two integer registers starting at an even register number, probably skipping one odd register.
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82 \item \$a0-\$a7 and \$f12-\$f19 are not required to be preserved.
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83 \item results are returned in \$v0 (32-bit integer), \$v0 and \$v1 (64-bit integer/float), \$f0 (32 bit float) and \$f0 and \$f2 (2 $\times$ 32 bit float e.g. complex).
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84 \end{itemize}
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85
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86 \paragraph{Stack layout}
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87
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88 Stack directly after function prolog:\\
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89
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90 \begin{figure}[h]
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91 \begin{tabular}{5|3|1 1}
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92 \hhline{~-~~}
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93 & \vdots & & \\
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94 \hhline{~=~~}
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95 register save area & & & \mrrbrace{5}{caller's frame} \\
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96 \hhline{~-~~}
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97 local data & & & \\
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98 \hhline{~-~~}
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99 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\
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100 & \ldots & & \\
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101 & \ldots & & \\
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102 \hhline{~=~~}
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103 register save area (with return address) & & & \mrrbrace{5}{current frame} \\
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104 \hhline{~-~~}
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105 local data & & & \\
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106 \hhline{~-~~}
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107 parameter area & & & \\
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108 \hhline{~-~~}
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109 & \vdots & & \\
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110 \hhline{~-~~}
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111 \end{tabular}
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112 \\
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113 \\
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114 \\
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115 \caption{Stack layout on mips32 eabi calling convention}
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116 \end{figure}
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117
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