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+ − 1 %//////////////////////////////////////////////////////////////////////////////
+ − 2 %
+ − 3 % Copyright (c) 2007,2009 Daniel Adler <dadler@uni-goettingen.de>,
+ − 4 % Tassilo Philipp <tphilipp@potion-studios.com>
+ − 5 %
+ − 6 % Permission to use, copy, modify, and distribute this software for any
+ − 7 % purpose with or without fee is hereby granted, provided that the above
+ − 8 % copyright notice and this permission notice appear in all copies.
+ − 9 %
+ − 10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ − 11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ − 12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ − 13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ − 14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ − 15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ − 16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ − 17 %
+ − 18 %//////////////////////////////////////////////////////////////////////////////
+ − 19
+ − 20 \subsection{MIPS Calling Convention}
+ − 21
+ − 22 \paragraph{Overview}
+ − 23
+ − 24 The MIPS family of processors is based on the MIPS processor architecture.
+ − 25 Multiple revisions of the MIPS Instruction set exist, namely MIPS I, MIPS II, MIPS III, MIPS IV, MIPS32 and MIPS64.
+ − 26 Today, MIPS32 and MIPS64 for 32-bit and 64-bit respectively.\\
+ − 27 Several add-on extensions exist for the MIPS family:
+ − 28
+ − 29 \begin{description}
+ − 30 \item [MIPS-3D] simple floating-point SIMD instructions dedicated to common 3D tasks.
+ − 31 \item [MDMX] (MaDMaX) more extensive integer SIMD instruction set using 64 bit floating-point registers.
+ − 32 \item [MIPS16e] adds compression to the instruction stream to make programs take up less room (allegedly a response to the THUMB instruction set of the ARM architecture).
+ − 33 \item [MIPS MT] multithreading additions to the system similar to HyperThreading.
+ − 34 \end{description}
+ − 35
+ − 36 Unfortunately, there is actually no such thing as "The MIPS Calling Convention". Many possible conventions are used
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+ − 37 by many different environments such as \emph{O32}, \emph{O64}, \emph{N32}, \emph{N64} and \emph{EABI}.\\
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+ − 38
+ − 39 \paragraph{\product{dyncall} support}
+ − 40
+ − 41 Currently, dyncall supports the EABI calling convention which is used on the Homebrew SDK for the Playstation Portable.
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+ − 42 As documentation for this EABI is unofficial, this port is currently experimental. It also supports O32, N32 and N64.
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+ − 43
+ − 44 \subsubsection{MIPS EABI 32-bit Calling Convention}
+ − 45
+ − 46 \paragraph{Register usage}
+ − 47
+ − 48 \begin{table}[h]
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+ − 49 \begin{tabular*}{0.95\textwidth}{lll}
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+ − 50 Name & Alias & Brief description\\
+ − 51 \hline
+ − 52 {\bf \$0} & {\bf \$zero} & Hardware zero \\
+ − 53 {\bf \$1} & {\bf \$at} & Assembler temporary \\
+ − 54 {\bf \$2-\$3} & {\bf \$v0-\$v1} & Integer results \\
+ − 55 {\bf \$4-\$11} & {\bf \$a0-\$a7} & Integer arguments\\
+ − 56 {\bf \$12-\$15,\$24,\$25} & {\bf \$t4-\$t7,\$t8,\$t9} & Integer temporaries \\
+ − 57 {\bf \$25} & {\bf \$t9} & Integer temporary, hold the address of the called function for all PIC calls (by convention) \\
+ − 58 {\bf \$16-\$23} & {\bf \$s0-\$s7} & Preserved \\
+ − 59 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & Reserved for kernel \\
+ − 60 {\bf \$28} & {\bf \$gp} & Global pointer \\
+ − 61 {\bf \$29} & {\bf \$sp} & Stack pointer \\
+ − 62 {\bf \$30} & {\bf \$s8} & Frame pointer \\
+ − 63 {\bf \$31} & {\bf \$ra} & Return address \\
+ − 64 {\bf hi, lo} & & Multiply/divide special registers \\
+ − 65 {\bf \$f0,\$f2} & & Float results \\
+ − 66 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & Float temporaries \\
+ − 67 {\bf \$f12-\$f19} & & Float arguments \\
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+ − 68 \end{tabular*}
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+ − 69 \caption{Register usage on mips32 eabi calling convention}
+ − 70 \end{table}
+ − 71
+ − 72 \paragraph{Parameter passing}
+ − 73
+ − 74 \begin{itemize}
+ − 75 \item Stack parameter order: right-to-left
+ − 76 \item Caller cleans up the stack
+ − 77 \item Stack always aligned to 8 bytes.
+ − 78 \item first 8 integers and floats are passed independently in registers using \$a0-\$a7 and \$f12-\$f19, respectively.
+ − 79 \item if either integer or float registers are consumed up, the stack is used.
+ − 80 \item 64-bit floats and integers are passed on two integer registers starting at an even register number, probably skipping one odd register.
+ − 81 \item \$a0-\$a7 and \$f12-\$f19 are not required to be preserved.
+ − 82 \item results are returned in \$v0 (32-bit integer), \$v0 and \$v1 (64-bit integer/float), \$f0 (32 bit float) and \$f0 and \$f2 (2 $\times$ 32 bit float e.g. complex).
+ − 83 \end{itemize}
+ − 84
+ − 85 \paragraph{Stack layout}
+ − 86
+ − 87 Stack directly after function prolog:\\
+ − 88
+ − 89 \begin{figure}[h]
+ − 90 \begin{tabular}{5|3|1 1}
+ − 91 \hhline{~-~~}
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+ − 92 & \vdots & & \\
+ − 93 \hhline{~=~~}
+ − 94 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\
+ − 95 \hhline{~-~~}
+ − 96 local data & & & \\
+ − 97 \hhline{~-~~}
+ − 98 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\
+ − 99 & \ldots & & \\
+ − 100 & \ldots & & \\
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+ − 101 \hhline{~=~~}
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+ − 102 register save area (with return address) & & & \mrrbrace{5}{current frame} \\
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+ − 103 \hhline{~-~~}
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+ − 104 local data & & & \\
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+ − 105 \hhline{~-~~}
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+ − 106 parameter area & & & \\
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+ − 107 \hhline{~-~~}
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+ − 108 & \vdots & & \\
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+ − 109 \hhline{~-~~}
+ − 110 \end{tabular}
+ − 111 \\
+ − 112 \\
+ − 113 \\
+ − 114 \caption{Stack layout on mips32 eabi calling convention}
+ − 115 \end{figure}
+ − 116
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+ − 117 \subsubsection{MIPS O32 32-bit Calling Convention}
+ − 118
+ − 119 @@@
+ − 120
+ − 121 \subsubsection{MIPS N32 32-bit Calling Convention}
+ − 122
+ − 123 @@@
+ − 124
