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- review and fixes, cleanup, amendments to calling convention appendix of manual
author Tassilo Philipp
date Fri, 22 Nov 2019 23:11:56 +0100
parents cde7b1f3b8f2
children 74c056b597b7
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1 %////////////////////////////////////////////////////////////////////////////// 1 %//////////////////////////////////////////////////////////////////////////////
2 % 2 %
3 % Copyright (c) 2007,2009 Daniel Adler <dadler@uni-goettingen.de>, 3 % Copyright (c) 2007-2019 Daniel Adler <dadler@uni-goettingen.de>,
4 % Tassilo Philipp <tphilipp@potion-studios.com> 4 % Tassilo Philipp <tphilipp@potion-studios.com>
5 % 5 %
6 % Permission to use, copy, modify, and distribute this software for any 6 % Permission to use, copy, modify, and distribute this software for any
7 % purpose with or without fee is hereby granted, provided that the above 7 % purpose with or without fee is hereby granted, provided that the above
8 % copyright notice and this permission notice appear in all copies. 8 % copyright notice and this permission notice appear in all copies.
18 %////////////////////////////////////////////////////////////////////////////// 18 %//////////////////////////////////////////////////////////////////////////////
19 19
20 % ================================================== 20 % ==================================================
21 % PowerPC 32 21 % PowerPC 32
22 % ================================================== 22 % ==================================================
23 \subsection{PowerPC (32bit) Calling Convention} 23 \subsection{PowerPC (32bit) Calling Conventions}
24 24
25 \paragraph{Overview} 25 \paragraph{Overview}
26 26
27 \begin{itemize} 27 \begin{itemize}
28 \item Word size is 32 bits 28 \item Word size is 32 bits
33 \item PowerPC EABI is defined in the "PowerPC Embedded Application Binary Interface 32-Bit Implementation". 33 \item PowerPC EABI is defined in the "PowerPC Embedded Application Binary Interface 32-Bit Implementation".
34 \end{itemize} 34 \end{itemize}
35 35
36 \paragraph{\product{dyncall} support} 36 \paragraph{\product{dyncall} support}
37 37
38 \product{Dyncall} and \product{dyncallback} are supported for PowerPC (32bit) Big Endian (MSB) on Darwin (tested on Apple Mac OS X) and Linux, however, fail for *BSD. 38 \product{Dyncall} and \product{dyncallback} are supported for PowerPC (32bit) Big Endian (MSB), for Darwin's and System V's calling convention.
39 39
40 40
41 \subsubsection{Mac OS X/Darwin} 41 \subsubsection{Mac OS X/Darwin}
42 42
43 \paragraph{Registers and register usage} 43 \paragraph{Registers and register usage}
47 Name & Brief description\\ 47 Name & Brief description\\
48 \hline 48 \hline
49 {\bf gpr0} & scratch\\ 49 {\bf gpr0} & scratch\\
50 {\bf gpr1} & stack pointer\\ 50 {\bf gpr1} & stack pointer\\
51 {\bf gpr2} & scratch\\ 51 {\bf gpr2} & scratch\\
52 {\bf gpr3,gpr4} & return value, parameter 0 and 1 for integer or pointer\\ 52 {\bf gpr3,gpr4} & return value, parameter 0 and 1 for integer or pointer, scratch\\
53 {\bf gpr5-gpr10} & parameter 2-7 for integer or pointer parameters\\ 53 {\bf gpr5-gpr10} & parameter 2-7 for integer or pointer parameters, scratch\\
54 {\bf gpr11} & permanent\\ 54 {\bf gpr11} & preserve\\
55 {\bf gpr12} & branch target for dynamic code generation\\ 55 {\bf gpr12} & branch target for dynamic code generation\\
56 {\bf gpr13-31} & permanent\\ 56 {\bf gpr13-31} & preserve\\
57 {\bf fpr0} & scratch\\ 57 {\bf fpr0} & scratch\\
58 {\bf fpr1} & floating point return value, floating point parameter 0 (always double precision)\\ 58 {\bf fpr1} & floating point return value, floating point parameter 0 (always double precision)\\
59 {\bf fpr2-fpr13} & floating point parameters 1-12 (always double precision)\\ 59 {\bf fpr2-fpr13} & floating point parameters 1-12 (always double precision)\\
60 {\bf fpr14-fpr31} & permanent\\ 60 {\bf fpr14-fpr31} & preserve\\
61 {\bf v0-v1} & scratch\\ 61 {\bf v0-v1} & scratch\\
62 {\bf v2-v13} & vector parameters\\ 62 {\bf v2-v13} & vector parameters\\
63 {\bf v14-v19} & scratch\\ 63 {\bf v14-v19} & scratch\\
64 {\bf v20-v31} & permanent\\ 64 {\bf v20-v31} & preserve\\
65 {\bf lr} & scratch, link-register\\ 65 {\bf lr} & link-register, scratch\\
66 {\bf ctr} & scratch, count-register\\ 66 {\bf ctr} & count-register, scratch\\
67 {\bf cr0-cr1} & scratch\\ 67 {\bf cr0-cr7} & conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\
68 {\bf cr2-cr4} & permanent\\
69 {\bf cr5-cr7} & scratch\\
70 \end{tabular*} 68 \end{tabular*}
71 \caption{Register usage on Darwin PowerPC 32-Bit} 69 \caption{Register usage on Darwin PowerPC 32-Bit}
72 \end{table} 70 \end{table}
73 71
74 \paragraph{Parameter passing} 72 \paragraph{Parameter passing}
75 73
76 \begin{itemize} 74 \begin{itemize}
75 \item stack grows down
77 \item stack parameter order: right-to-left 76 \item stack parameter order: right-to-left
78 \item caller cleans up the stack 77 \item caller cleans up the stack
79 \item the first 8 integer parameters are passed in registers gpr3-gpr10 78 \item the first 8 integer parameters are passed in registers gpr3-gpr10
80 \item the first 12 floating point parameters are passed in registers fpr1-fpr13 79 \item the first 12 floating point parameters are passed in registers fpr1-fpr13
80 \item 64 bit arguments are passed as if they were two 32 bit arguments, without skipping registers for alignment (this means passing half via a register and half via the stack is allowed)
81 \item if a float parameter is passed via a register, gpr registers are skipped for subsequent integer parameters (based on the size of 81 \item if a float parameter is passed via a register, gpr registers are skipped for subsequent integer parameters (based on the size of
82 the float - 1 register for single precision and 2 for double precision floating point values) 82 the float - 1 register for single precision and 2 for double precision floating point values)
83 \item the caller pushes subsequent parameters onto the stack 83 \item the caller pushes subsequent parameters onto the stack
84 \item for every parameter passed via a register, space is reserved in the stack parameter area (in order to spill the parameters if 84 \item for every parameter passed via a register, space is reserved in the stack parameter area (in order to spill the parameters if
85 needed - e.g. varargs) 85 needed - e.g. varargs)
102 \item floating point values are returned via fpr1 102 \item floating point values are returned via fpr1
103 \item structures \textless=\ 64 bits use gpr3 and gpr4 103 \item structures \textless=\ 64 bits use gpr3 and gpr4
104 \item for types \textgreater\ 64 bits, a secret first parameter with an address to the return value is passed 104 \item for types \textgreater\ 64 bits, a secret first parameter with an address to the return value is passed
105 \end{itemize} 105 \end{itemize}
106 106
107 \pagebreak
108 107
109 \paragraph{Stack layout} 108 \paragraph{Stack layout}
110 109
111 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\ 110 % verified/amended: TP nov 2019 (see also doc/disas_examples/ppc.darwin.disas)
111 Stack frame is always 16-byte aligned. Prolog opens frame with additional, fixed space for a linkage area, to hold a number of values (not all of them are required to be saved, though). Stack directly after function prolog:\\
112 112
113 \begin{figure}[h] 113 \begin{figure}[h]
114 \begin{tabular}{5|3|1 1} 114 \begin{tabular}{5|3|1 1}
115 \hhline{~-~~} 115 & \vdots & & \\
116 & \vdots & & \\ 116 \hhline{~=~~}
117 \hhline{~=~~} 117 register save area & \hspace{4cm} & & \mrrbrace{14}{caller's frame} \\
118 local data & \hspace{4cm} & & \mrrbrace{13}{caller's frame} \\ 118 \hhline{~-~~}
119 \hhline{~-~~} 119 local data & & & \\
120 \mrlbrace{6}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ 120 \hhline{~-~~}
121 & \ldots & & \\ 121 \mrlbrace{6}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\
122 & \ldots & & \\ 122 & \ldots & & \\
123 & \ldots & \mrrbrace{3}{spill area (as needed)} & \\ 123 & 9th word of arg data & & \\
124 & \ldots & & \\ 124 & gpr10 & \mrrbrace{3}{spill area (as needed)} & \\
125 & gpr3 or fpr1 & & \\ 125 & \ldots & & \\
126 \hhline{~-~~} 126 & gpr3 & & \\
127 \mrlbrace{6}{linkage area} & reserved & & \\ 127 \hhline{~-~~}
128 & reserved & & \\ 128 \mrlbrace{6}{linkage area} & reserved & & \\
129 & reserved & & \\ 129 & reserved & & \\
130 & return address & & \\ 130 & reserved & & \\
131 & reserved for callee & & \\ 131 & return address (callee saved) & & \\
132 & saved by callee & & \\ 132 & condition reg (callee saved) & & \\
133 \hhline{~=~~} 133 & parent stack frame pointer & & \\
134 local data & & & \mrrbrace{3}{current frame} \\ 134 \hhline{~=~~}
135 \hhline{~-~~} 135 register save area & & & \mrrbrace{4}{current frame} \\
136 parameter area & & & \\ 136 \hhline{~-~~}
137 \hhline{~-~~} 137 local data & & & \\
138 linkage area & \vdots & & \\ 138 \hhline{~-~~}
139 \hhline{~-~~} 139 parameter area & & & \\
140 \hhline{~-~~}
141 linkage area & \vdots & & \\
140 \end{tabular} 142 \end{tabular}
141 \caption{Stack layout on ppc32 Darwin} 143 \caption{Stack layout on ppc32 Darwin}
142 \end{figure} 144 \end{figure}
143 145
146
147 \newpage
148
149
144 \subsubsection{System V PPC 32-bit} 150 \subsubsection{System V PPC 32-bit}
145 151
146 \paragraph{Status} 152 \paragraph{Status}
147
148 \begin{itemize}
149 \item C++ this calls do not work.
150 \end{itemize}
151 153
152 \paragraph{Registers and register usage} 154 \paragraph{Registers and register usage}
153 155
154 \begin{table}[h] 156 \begin{table}[h]
155 \begin{tabular*}{0.95\textwidth}{3 B} 157 \begin{tabular*}{0.95\textwidth}{3 B}
156 Name & Brief description\\ 158 Name & Brief description\\
157 \hline 159 \hline
158 {\bf r0} & scratch\\ 160 {\bf r0} & scratch\\
159 {\bf r1} & stack pointer\\ 161 {\bf r1} & stack pointer, preserve\\
160 {\bf r2} & system-reserved\\ 162 {\bf r2} & system-reserved\\
161 {\bf r3-r4} & parameter passing and return value\\ 163 {\bf r3-r4} & parameter passing and return value, scratch\\
162 {\bf r5-r10} & parameter passing\\ 164 {\bf r5-r10} & parameter passing, scratch\\
163 {\bf r11-r12} & scratch\\ 165 {\bf r11-r12} & scratch\\
164 {\bf r13} & Small data area pointer register\\ 166 {\bf r13} & small data area pointer register\\
165 {\bf r14-r30} & Local variables\\ 167 {\bf r14-r30} & local variables, preserve\\
166 {\bf r31} & Used for local variables or \emph{environment pointer}\\ 168 {\bf r31} & used for local variables or \emph{environment pointer}, preserve\\
167 {\bf f0} & scratch\\ 169 {\bf f0} & scratch\\
168 {\bf f1} & parameter passing and return value\\ 170 {\bf f1} & parameter passing and return value, scratch\\
169 {\bf f2-f8} & parameter passing\\ 171 {\bf f2-f8} & parameter passing, scratch\\
170 {\bf f9-13} & scratch\\ 172 {\bf f9-13} & scratch\\
171 {\bf f14-f31} & Local variables\\ 173 {\bf f14-f31} & local variables, preserve\\
172 {\bf cr0-cr7} & Conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\ 174 {\bf cr0-cr7} & conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\
173 {\bf lr} & Link register (scratch)\\ 175 {\bf lr} & link register, scratch\\
174 {\bf ctr} & Count register (scratch) \\ 176 {\bf ctr} & count register, scratch \\
175 {\bf xer} & Fixed-point exception register (scratch)\\ 177 {\bf xer} & fixed-point exception register, scratch\\
176 {\bf fpscr} & Floating-point Status and Control Register\\ 178 {\bf fpscr} & floating-point Status and Control Register\\
177 % {\bf v0-v1} & scratch\\ 179 % {\bf v0-v1} & scratch\\
178 % {\bf v2-v13} & vector parameters\\ 180 % {\bf v2-v13} & vector parameters\\
179 % {\bf v14-v19} & scratch\\ 181 % {\bf v14-v19} & scratch\\
180 % {\bf v20-v31} & permanent\\ 182 % {\bf v20-v31} & permanent\\
181 % {\bf lr} & scratch, link-register\\ 183 % {\bf lr} & scratch, link-register\\
193 \item Stack pointer (r1) is always 16-byte aligned. The EABI differs here - it is 8-byte alignment. 195 \item Stack pointer (r1) is always 16-byte aligned. The EABI differs here - it is 8-byte alignment.
194 \item 8 general-purpose registers (r3-r10) for integer and pointer types. 196 \item 8 general-purpose registers (r3-r10) for integer and pointer types.
195 \item 8 floating-pointer registers (f1-f8) for float (promoted to double) and double types. 197 \item 8 floating-pointer registers (f1-f8) for float (promoted to double) and double types.
196 \item Additional arguments are passed on the stack directly after the back-chain and saved return address (8 bytes structure) on the callers stack frame. 198 \item Additional arguments are passed on the stack directly after the back-chain and saved return address (8 bytes structure) on the callers stack frame.
197 \item 64-bit integer data types are passed in general-purpose registers as a whole in two 199 \item 64-bit integer data types are passed in general-purpose registers as a whole in two
198 32-bit general purpose registers (an odd and an even e.g. r3 and r4), probably skipping an even integer register. 200 32-bit general purpose registers (an odd and an even e.g. r3 and r4), skipping an even integer register
199 or passed on the stack. They are never splitted into a register and stack part. 201 or passed on the stack; they are never splitted into a register and stack part
200 \item Ellipse calls set CR bit 6 202 \item Ellipse calls set CR bit 6
201 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy high-order bytes) in their 4-byte area, requiring extra-care for big-endian targets 203 \item integer parameters \textless\ 32 bit are right-justified (meaning occupy high-order bytes) in their 4-byte area, requiring extra-care for big-endian targets
204 \item no spill area is used on stack, iterating over varargs requires a specific va\_list implementation
202 \end{itemize} 205 \end{itemize}
203 206
204 \paragraph{Return values} 207 \paragraph{Return values}
205 208
206 \begin{itemize} 209 \begin{itemize}
207 \item 32-bit integers use register r3, 64-bit use registers r3 and r4 (hiword in r3, loword in r4). 210 \item 32-bit integers use register r3, 64-bit use registers r3 and r4 (hiword in r3, loword in r4).
208 \item floating-point values are returned using register f1. 211 \item floating-point values are returned using register f1.
209 \end{itemize} 212 \end{itemize}
210 213
211 \pagebreak
212 214
213 \paragraph{Stack layout} 215 \paragraph{Stack layout}
214 216
217 % verified/amended: TP nov 2019 (see also doc/disas_examples/ppc.sysv.disas)
215 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\ 218 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\
216 219
217 \begin{figure}[h] 220 \begin{figure}[h]
218 \begin{tabular}{5|3|1 1} 221 \begin{tabular}{5|3|1 1}
219 \hhline{~-~~} 222 & \vdots & & \\
220 & \vdots & & \\ 223 \hhline{~=~~}
221 \hhline{~=~~} 224 register save area & \hspace{4cm} & & \mrrbrace{7}{caller's frame} \\
222 local data & \hspace{4cm} & & \mrrbrace{6}{caller's frame} \\ 225 \hhline{~-~~}
223 \hhline{~-~~} 226 local data & & & \\
224 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ 227 \hhline{~-~~}
225 & \ldots & & \\ 228 \mrlbrace{3}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\
226 & \ldots & & \\ 229 & \ldots & & \\
227 \hhline{~-~~} 230 & first arg passed via stack & & \\
228 & saved return address (for callee) & & \\ 231 \hhline{~-~~}
229 \hhline{~-~~} 232 & return address (callee saved) & & \\
230 & parent stack frame pointer & & \\ 233 \hhline{~-~~}
231 \hhline{~=~~} 234 & parent stack frame pointer & & \\
232 local data & & & \mrrbrace{3}{current frame} \\ 235 \hhline{~=~~}
233 \hhline{~-~~} 236 register save area & & & \mrrbrace{4}{current frame} \\
234 parameter area & & & \\ 237 \hhline{~-~~}
235 \hhline{~-~~} 238 local data & & & \\
236 & \vdots & & \\ 239 \hhline{~-~~}
237 \hhline{~-~~} 240 parameter area & & & \\
241 \hhline{~-~~}
242 & \vdots & & \\
238 \end{tabular} 243 \end{tabular}
239 \\
240 \\
241 \\
242 \caption{Stack layout on System V ABI for PowerPC 32-bit calling convention} 244 \caption{Stack layout on System V ABI for PowerPC 32-bit calling convention}
243 \end{figure} 245 \end{figure}
246