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+%//////////////////////////////////////////////////////////////////////////////
+%
+% Copyright (c) 2012 Daniel Adler <dadler@uni-goettingen.de>, 
+%                    Tassilo Philipp <tphilipp@potion-studios.com>
+%
+% Permission to use, copy, modify, and distribute this software for any
+% purpose with or without fee is hereby granted, provided that the above
+% copyright notice and this permission notice appear in all copies.
+%
+% THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+% WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+% MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+% ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+% WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+% ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+% OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+%
+%//////////////////////////////////////////////////////////////////////////////
+
+\subsection{SPARC Calling Convention}
+
+\paragraph{Overview}
+
+The SPARC family of processors is based on the SPARC instruction set architecture, which comes in basically tree revisions,
+V7, V8 and V9. The former two are 32-bit whereas the latter refers to the 64-bit SPARC architecture (see next chapter). SPARC is big endian.
+
+\paragraph{\product{dyncall} support}
+
+\product{dyncall} fully supports the SPARC 32-bit instruction set (V7 and V8), \product{dyncallback} support is missing, though.
+
+\subsubsection{SPARC (32-bit) Calling Convention}
+
+\paragraph{Register usage}
+
+\begin{itemize}
+\item 32 32-bit integer/pointer registers
+\item 32 floating point registers (usable as 8 quad precision, 16 double precision or 32 single precision registers)
+\item 32 registers are accessible at a time (8 are global ones (g*), whereas the rest forms a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones)
+\item invoking a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore)
+\end{itemize}
+
+\begin{table}[h]
+\begin{tabular}{lll}
+\hline
+Name                                 & Alias                   & Brief description\\
+\hline
+{\bf \%g0}                           &                         & Read-only, hardwired to 0 \\
+{\bf \%g1-\%g7}                      &                         & Global \\
+{\bf \%o0 and \%i0}                  &                         & Output and input argument 0, return value \\
+{\bf \%o1-\%o5 and \%i1-\%i5}        &                         & Output and input argument registers \\
+{\bf \%o6 and \%i6}                  &                         & Stack and frame pointer \\
+{\bf \%o7 and \%i7}                  &                         & Return address (caller writes to o7, callee uses i7) \\
+\end{tabular}
+\caption{Register usage on sparc calling convention}
+\end{table}
+
+\paragraph{Parameter passing}
+\begin{itemize}
+\item Stack parameter order: right-to-left @@@ really?
+\item Caller cleans up the stack @@@ really?
+\item Stack always aligned to 8 bytes.
+\item first 6 integers and floats are passed independently in registers using \%o0-\%o5
+\item for every other argument the stack is used
+\item @@@ what about floats, 64bit integers, etc.?
+\item results are returned in \%i0, and structs/unions pass a pointer to them as a hidden stack parameter (see below)
+\end{itemize}
+
+\paragraph{Stack layout}
+
+Stack directly after function prolog:\\
+
+\begin{figure}[h]
+\begin{tabular}{5|3|1 1}
+\hhline{~-~~}
+                                   & \vdots                      &                                &                               \\
+\hhline{~=~~}
+local data                         &                             &                                & \mrrbrace{10}{caller's frame} \\
+\hhline{~-~~}
+padding                            &                             &                                &                               \\
+\hhline{~-~~}
+\mrlbrace{7}{parameter area}       & argument x                  & \mrrbrace{3}{stack parameters} &                               \\
+                                   & \ldots                      &                                &                               \\
+                                   & argument 6                  &                                &                               \\
+                                   & input argument 5 spill      & \mrrbrace{3}{spill area}       &                               \\
+                                   & \ldots                      &                                &                               \\
+                                   & input argument 0 spill      &                                &                               \\
+                                   & struct/union return pointer &                                &                               \\
+\hhline{~-~~}
+register save area (\%i* and \%l*) &                             &                                &                               \\
+\hhline{~=~~}
+local data and padding             &                             &                                & \mrrbrace{3}{current frame}   \\
+\hhline{~-~~}
+parameter area                     &                             &                                &                               \\
+\hhline{~-~~}
+                                   & \vdots                      &                                &                               \\
+\hhline{~-~~}
+\end{tabular}
+\\
+\\
+\\
+\caption{Stack layout on sparc calling convention}
+\end{figure}
+