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- review and fixes, cleanup, amendments to calling convention appendix of manual
author Tassilo Philipp
date Fri, 22 Nov 2019 23:11:56 +0100
parents 4a64b733dc76
children bac52ab8869f
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327:c0390dc85a07 328:276eb8c87aa0
1 %//////////////////////////////////////////////////////////////////////////////
1 % 2 %
2 % Copyright (c) 2014,2015 Daniel Adler <dadler@uni-goettingen.de>, 3 % Copyright (c) 2014-2019 Daniel Adler <dadler@uni-goettingen.de>,
3 % Tassilo Philipp <tphilipp@potion-studios.com> 4 % Tassilo Philipp <tphilipp@potion-studios.com>
4 % 5 %
5 % Permission to use, copy, modify, and distribute this software for any 6 % Permission to use, copy, modify, and distribute this software for any
6 % purpose with or without fee is hereby granted, provided that the above 7 % purpose with or without fee is hereby granted, provided that the above
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12 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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15 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 % 17 %
18 %//////////////////////////////////////////////////////////////////////////////
17 19
18 % ================================================== 20 % ==================================================
19 % ARM64 21 % ARM64
20 % ================================================== 22 % ==================================================
21 \subsection{ARM64 Calling Convention} 23 \subsection{ARM64 Calling Conventions}
22 24
23 \paragraph{Overview} 25 \paragraph{Overview}
24 26
25 ARMv8 introduced the AArch64 calling convention. ARM64 chips can be run in 64 or 32bit mode, but not by the same process. Interworking is only intra-process.\\ 27 ARMv8 introduced the AArch64 calling convention. ARM64 chips can be run in 64 or 32bit mode, but not by the same process. Interworking is only intra-process.\\
26 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due to historical reasons (terminology didn't change from ARM32).\\ 28 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due to historical reasons (terminology didn't change from ARM32).\\
27 For more details, take a look at the Procedure Call Standard for the ARM 64-bit Architecture \cite{AAPCS64}.\\ 29 For more details, take a look at the Procedure Call Standard for the ARM 64-bit Architecture \cite{AAPCS64}.\\
28 30
29 \paragraph{\product{dyncall} support} 31 \paragraph{\product{dyncall} support}
30 32
31 The \product{dyncall} library supports the ARM 64-bit AArch64 PCS ABI, for calls and callbacks. 33 The \product{dyncall} library supports the ARM 64-bit AArch64 PCS ABI, as well as Apple's convention derived from it, for calls and callbacks.
32 34
33 \subsubsection{AAPCS64 Calling Convention} 35 \subsubsection{AAPCS64 Calling Convention}
34 36
35 \paragraph{Registers and register usage} 37 \paragraph{Registers and register usage}
36 38
37 ARM64 features thirty-one 64 bit general purpose registers, namely x0-x30. 39 ARM64 features thirty-one 64 bit general purpose registers, namely {\bf r0-r30},
38 Also, there is SP, a register with restricted use, used for the stack pointer, 40 which are referred to as either {\bf x0-x30} for 64bit access, or {\bf w0-w30}
39 and PC dedicated as program counter. Additionally, there are thirty-two 128 bit 41 for 32bit access (with upper bits either cleared or sign extended on load).\\
40 registers v0-v31, to be used as SIMD and floating point registers, referred to 42 Also, there is {\bf sp/xzr/wzr}, a register with restricted use, used for the
41 as q0-q31, d0-d31 and s0-s31, respectively, depending on their use:\\ 43 stack pointer in instructions dealing with the stack ({\bf sp}) or a hardware
44 zero register for all other instructions {\bf xzr/wzr}, and {\bf pc}, the
45 program counter. Additionally, there are thirty-two 128 bit registers {\bf v0-v31},
46 to be used as SIMD and floating point registers, referred to as {\bf q0-q31}, {\bf d0-d31}
47 and {\bf s0-s31}, respectively, depending on their use:\\
42 48
43 \begin{table}[h] 49 \begin{table}[h]
44 \begin{tabular*}{0.95\textwidth}{3 B} 50 \begin{tabular*}{0.95\textwidth}{3 B}
45 Name & Brief description\\ 51 Name & Brief description\\
46 \hline 52 \hline
51 {\bf x17} & permanent in some cases, can have special function (IP1), see doc\\ 57 {\bf x17} & permanent in some cases, can have special function (IP1), see doc\\
52 {\bf x18} & reserved as platform register, advised not to be used for handwritten, portable asm, see doc \\ 58 {\bf x18} & reserved as platform register, advised not to be used for handwritten, portable asm, see doc \\
53 {\bf x19-x28} & permanent\\ 59 {\bf x19-x28} & permanent\\
54 {\bf x29} & permanent, frame pointer\\ 60 {\bf x29} & permanent, frame pointer\\
55 {\bf x30} & permanent, link register\\ 61 {\bf x30} & permanent, link register\\
56 {\bf SP} & permanent, stack pointer\\ 62 {\bf sp} & permanent, stack pointer\\
57 {\bf PC} & program counter\\ 63 {\bf pc} & program counter\\
58 \end{tabular*} 64 \end{tabular*}
59 \caption{Register usage on arm64} 65 \caption{Register usage on arm64}
60 \end{table} 66 \end{table}
61 67
62 \paragraph{Parameter passing} 68 \paragraph{Parameter passing}
65 \item stack parameter order: right-to-left 71 \item stack parameter order: right-to-left
66 \item caller cleans up the stack 72 \item caller cleans up the stack
67 \item first 8 integer arguments are passed using x0-x7 73 \item first 8 integer arguments are passed using x0-x7
68 \item first 8 floating point arguments are passed using d0-d7 74 \item first 8 floating point arguments are passed using d0-d7
69 \item subsequent parameters are pushed onto the stack 75 \item subsequent parameters are pushed onto the stack
70 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first 8 integer and 8 floating-point registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed parameters require saving, though) 76 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first 8 integer and 8 floating-point registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed integer parameters require saving, though)
71 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3 77 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3
72 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc... (see {\bf return values}) 78 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc... (see {\bf return values})
73 \item stack is required to be throughout eight-byte aligned 79 \item stack is required to be throughout eight-byte aligned
74 \end{itemize} 80 \end{itemize}
75 81
80 \item otherwise, the caller allocates space, passes pointer to it to the callee through x8, and callee writes return value to this space 86 \item otherwise, the caller allocates space, passes pointer to it to the callee through x8, and callee writes return value to this space
81 \end{itemize} 87 \end{itemize}
82 88
83 \paragraph{Stack layout} 89 \paragraph{Stack layout}
84 90
91 % verified/amended: TP nov 2019 (see also doc/disas_examples/arm64.aapcs.disas)
85 Stack directly after function prolog:\\ 92 Stack directly after function prolog:\\
86 93
87 \begin{figure}[h] 94 \begin{figure}[h]
88 \begin{tabular}{5|3|1 1} 95 \begin{tabular}{5|3|1 1}
89 \hhline{~-~~} 96 & \vdots & & \\
90 & \vdots & & \\
91 \hhline{~=~~} 97 \hhline{~=~~}
92 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ 98 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\
93 \hhline{~-~~} 99 \hhline{~-~~}
94 local data & & & \\ 100 local data & & & \\
95 \hhline{~-~~} 101 \hhline{~-~~}
96 \mrlbrace{13}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ 102 \mrlbrace{9}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\
97 & \ldots & & \\ 103 & \ldots & & \\
98 & \ldots & & \\ 104 & arg 8 & & \\
99 \hhline{~=~~} 105 \hhline{~=~~}
100 & x0 & \mrrbrace{10}{spill area (if needed)} & \mrrbrace{15}{current frame} \\ 106 & x7 & \mrrbrace{6}{spill area (if needed)} & \mrrbrace{9}{current frame} \\
101 & x1 & & \\ 107 & \ldots & & \\
102 & \ldots & & \\ 108 & x? (first unnamed reg) & & \\
103 & x2 & & \\ 109 & q7 & & \\
104 & x7 & & \\ 110 & \ldots & & \\
105 & d0 & & \\ 111 & q0 & & \\
106 & d1 & & \\
107 & \ldots & & \\
108 & d2 & & \\
109 & d7 & & \\
110 \hhline{~-~~} 112 \hhline{~-~~}
111 register save area & & & \\ 113 register save area (with return address) & & & \\ % fp will point here (to 1st arg) @@@ verify
112 \hhline{~-~~} 114 \hhline{~-~~}
113 local data & & & \\ 115 local data & & & \\
114 \hhline{~-~~} 116 \hhline{~-~~}
115 link and frame register & x30 & & \\ 117 parameter area & \vdots & & \\
116 & x29 & & \\
117 \hhline{~-~~}
118 parameter area & \vdots & & \\
119 \hhline{~-~~}
120 \end{tabular} 118 \end{tabular}
121 \caption{Stack layout on arm64} 119 \caption{Stack layout on arm64}
122 \end{figure} 120 \end{figure}
123 121
124 \newpage 122 \newpage