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- doc and disasexample additions specific to non-trivial C++ aggregates as return values (incl. fixes to doc and additional LSB specific PPC32 section)
author Tassilo Philipp
date Mon, 04 Apr 2022 15:50:52 +0200
parents 6c72cb768099
children 9d0eefb0e0f0
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1 %//////////////////////////////////////////////////////////////////////////////
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2 %
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3 % Copyright (c) 2012-2022 Daniel Adler <dadler@uni-goettingen.de>,
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4 % Tassilo Philipp <tphilipp@potion-studios.com>
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5 %
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6 % Permission to use, copy, modify, and distribute this software for any
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7 % purpose with or without fee is hereby granted, provided that the above
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8 % copyright notice and this permission notice appear in all copies.
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9 %
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10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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17 %
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18 %//////////////////////////////////////////////////////////////////////////////
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19
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20 \subsection{SPARC64 Calling Conventions}
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21
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22 \paragraph{Overview}
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23
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24 The SPARC family of processors is based on the SPARC instruction set architecture, which comes in basically three revisions,
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25 V7, V8\cite{SPARCV8}\cite{SPARCSysV}\cite{SPARCCD} and V9\cite{SPARCV9}\cite{SPARCV9SysV}\cite{SPARCCD}. The former two are 32-bit (see previous chapter) whereas the latter refers to the 64-bit SPARC architecture.
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26 SPARC uses big endian byte order, however, V9 supports also little endian byte order, but for data access only, not instruction access.\\
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27 \\
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28 There are two proposals, one from Sun and one from Hal, which disagree on how to handle some aspects of this calling convention.\\
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29
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30 \paragraph{\product{dyncall} support}
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31
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32 \product{dyncall} fully supports the SPARC 64-bit instruction set (V9), for calls and callbacks.
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34 \subsubsection{SPARC (64-bit) Calling Convention}
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35
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36 \begin{itemize}
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37 \item 32 double precision floating point registers (d0,d2,d4,...,d62, usable as 16 quad precision ones q0,q4,q8,...g60, and also first half of them are usable as 32 single precision registers f0-f31)
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38 \item 32 64-bit integer/pointer registers out of a bigger (vendor/model dependent) number that are accessible at a time (8 are global ones (g*), whereas the remaining 24 form a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones)
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39 \item calling a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore)
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40 \item stack and frame pointer are offset by a BIAS of 2047 (see official doc for reasons)
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41 \end{itemize}
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42
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43 \begin{table}[h]
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44 \begin{tabular*}{0.95\textwidth}{lll}
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45 Name & Alias & Brief description\\
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46 \hline
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47 {\bf \%g0} & \%r0 & Read-only, hardwired to 0 \\
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48 {\bf \%g1-\%g7} & \%r1-\%r7 & Global \\
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49 {\bf \%o0-\%o3 and \%i0-\%i3} & \%r8-\%r11 and \%r24-\%r27 & Output and input argument registers, return value \\
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50 {\bf \%o4,\%o5 and \%i4,\%i5} & \%r12,\%r13 and \%r28,\%r29 & Output and input argument registers \\
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51 {\bf \%o6 and \%i6} & \%r14 and \%r30, \%sp and \%fp & Stack and frame pointer (NOTE, offset with a BIAS of 2047) \\
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52 {\bf \%o7 and \%i7} & \%r15 and \%r31 & Return address (caller writes to o7, callee uses i7) \\
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53 {\bf \%l0-\%l7} & \%r16-\%r23 & preserve \\
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54 {\bf \%d0,\%d2,\%d4,\%d6} & & scratch, Floating point arguments, return value \\
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55 {\bf \%d8,\%d10,...,\%d14} & & scratch, Floating point arguments \\
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56 {\bf \%d16,\%d18,...,\%d30} & & scratch (preserve for Hal), Floating point arguments \\
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57 {\bf \%d32,\%d34,...,\%d62} & & scratch (preserve for Hal) \\
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58 \end{tabular*}
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59 \caption{Register usage on sparc64 calling convention}
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60 \end{table}
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61
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62 \paragraph{Parameter passing}
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63 \begin{itemize}
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64 \item stack grows down
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65 \item stack parameter order: right-to-left
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66 \item caller cleans up the stack
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67 \item stack frame is always aligned to 16 bytes
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68 \item first 6 integers are passed in registers using \%o0-\%o5
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69 \item first 8 quad precision floating point args (or 16 double precision, or 32 single precision) are passed in floating point registers (\%q0,\%q4,...,\%q28 or \%d0,\%d2,...,\%d30 or \%f0-\%f31, respectively)
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70 \item for every other argument the stack is used
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71 \item single precision floating point args are passed in odd \%f* registers, and are "right aligned" in their 8-byte space on the stack
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72 \item for every argument passed, corresponding \%o*, \%f* register or stack space is skipped (e.g. passing a double as 3rd call argument, \%d4 is used and \%o2 is skipped)
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73 \item all arguments \textless=\ 64 bit are passed as 64 bit values
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74 \item minimum stack size is 128 bytes, b/c stack pointer must always point at enough space to store all \%i* and \%l* registers, used when running out of register windows
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75 \item if needed, register spill area (both, integer and float arguments are spilled in order) is adjacent to parameters
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76 \item structs with only one field are passed as if the param would be the field itself
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77 \item structs \textless=\ 16 bytes (which have more than one field) are passed field-by-field, {\bf however} evaluated as a sequence of 8-byte parameter slots
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78 \begin{itemize}
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79 \item note that due to aggregate alignment rules, any floating point value is either the entire slot (for double precision) or exactly one half
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80 \item fields are left justified in register or stack slots
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81 \item integers in a slot are passed as such (either via \%o* registers or the stack)
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82 \item single precision floats (using half of the slot) use even numbered \%f* registers when they occupy the left half, odd numbered ones otherwise (no register skipping logic applied within a slot)
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83 \item splitting struct fields between registers and stack is allowed
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84 \end{itemize}
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85 \item unions \textless=\ 16 bytes passed by-value are passed like integers in left-justified 8-byte slots (either via \%o* registers or the stack)
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86 \item aggregates (struct, union) and types \textgreater\ 16 bytes are passed indirectly, as a pointer to a correctly aligned copy of the data (that copy can be avoided under certain conditions)
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87 \item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate
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88 % from spec:
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89 %Structure or union types up to eight bytes in size are assigned to one parameter array word, and align to eight-byte
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90 %boundaries.
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91 %Structure or union types larger than eight bytes, and up to sixteen bytes in size are assigned to two consecutive
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92 %parameter array words, and align according to the alignment requirements of the structure or at least to an eight-byte
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93 %boundary.
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94 %Structure or union types are always left-justified, whether stored in registers or memory. The individual fields of a
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95 %structure (or containing storage unit in the case of bit fields) are subject to promotion into registers based on their type
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96 %using the same rules as apply to scalar values (with the addition that a single-precision floating-point number assigned
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97 %to the left half of an argument slot will be promoted into the corresponding even-numbered float register.). Any union
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98 %type being passed directly is subject to promotion into the appropriate integer register(s).
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99 %Note that a sixteen-byte structure with all integral fields assigned to locations %sp+BIAS+168 and %sp+BIAS+176 will
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100 %be “split,” as the contents of location %sp+BIAS+168 will be promoted to %o5.
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101 %Structures or unions larger than sixteen bytes are copied by the caller and passed indirectly; the caller will pass the
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102 %address of a correctly aligned structure value. This sixty-four bit address will occupy one word in the parameter array,
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103 %and may be promoted to an %o register like any other pointer value. The callee may modify the addressed structure.
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104 %The caller can omit the copy if such omission cannot be detected. That requires (at least) that:
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105 %* the original aggregate is already properly aligned,
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106 %* the original aggregate is not aliased,
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107 %* the original aggregate is not used after the call, and
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108 %* no language-specific semantics require the copy.
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109 \end{itemize}
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110
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111 \paragraph{Return values}
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112
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113 \begin{itemize}
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114 \item results are expected by caller to be returned in \%o0-\%o3 (after reg window restore, meaning callee writes to \%i0-\%i3) for integers
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115 \item \%d0,\%d2,\%d4,\%d6 are used for floating point values
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116 \item for {\it non-trivial} C++ aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param
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117 (meaning in \%o0), and callee writes return value to this space; the ptr to the aggregate is returned in the same register (after reg window restore)
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118 \item the fields of aggregates (struct, union) \textless= 32 bytes are returned via registers mentioned above (which are
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119 assigned following the same logic as when passing the aggregate as a first argument to a function)
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120 \item aggregates (struct, union) \textgreater 32 bytes are returned in a space allocated by the caller, with a pointer to it
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121 passed as first parameter to the function called (meaning in \%o0)
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122 % from spec:
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123 %Structure and union return types up to thirty-two bytes in size are returned in registers. The registers are assigned as if
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124 %the value was being passed as the first argument to a function with a known prototype.
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125 %For types with a larger size the caller allocates an area large enough and aligned properly to hold the return value, and
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126 %passes a pointer to that area as an implicit first argument (of type pointer-to-data) to the callee. This implicit argument
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127 %logically precedes the first actual argument, and is allocated according to normal argument passing rules (i.e. into %o0).
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128 %The callee must store the function return value in the result area before control is returned to the caller and after the last
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129 %use or definition of any variable that might overlap with the result area. If the callee is terminated through any means
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130 %other than a normal function return (e.g., through a call to the longjmp function), the contents of the result area are
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131 %undefined.
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132 %In the common case that the caller immediately assigns the returned value to a program variable, the caller may
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133 %substitute the address of the assigned program variable in place of the allocated result area and omit the code to do the
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134 %assignment, as long as this substitution does not change the program’s externally visible behavior.
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135 %Note also that the caller is required to provide the implicit argument and a properly sized and aligned receiving area
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136 %even if it does not wish to use the callee’s function result. In that case, the caller may simply pass a pointer to a scratch
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137 %area.
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138 %So that compilers are not forced to emit in-line code for structure copy, Section 6.2 defines a set of routines optimized
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139 %for this purpose. In the case of a routine which had kept its first argument in %i0 and was returning a value pointed to
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140 %by %i1, epilogue code would take the form:
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141 %
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142 %mov %i0, %o0
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143 %mov %i1, %o1
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144 %call __align_cpy_n
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145 %mov size, %o2
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146 %ret
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147 %restore %o0, %g0, %o0
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148 %
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149 \end{itemize}
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150
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151 \paragraph{Stack layout}
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152
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153 % verified/amended: TP nov 2019 (see also doc/disas_examples/sparc64.sparc64.disas)
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154 Stack directly after function prolog:\\
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155
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156 \begin{figure}[h]
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157 \begin{tabular}{5|3|1 1}
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158 & \vdots & & \\
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159 \hhline{~=~~}
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160 local data (and padding) & \hspace{4cm} & & \mrrbrace{8}{caller's frame} \\
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161 \hhline{~-~~}
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162 \mrlbrace{6}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\
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163 & \ldots & & \\
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164 & arg 6 & & \\
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165 & \%o5 & \mrrbrace{3}{spill area} & \\
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166 & \ldots & & \\
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167 & \%o0 & & \\
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168 \hhline{~-~~}
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169 register save area (\%i* and \%l*) & & & \\
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170 \hhline{~=~~}
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171 local data (and padding) & & & \mrrbrace{3}{current frame} \\
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172 \hhline{~-~~}
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173 parameter area & & & \\
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174 \hhline{~-~~}
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175 & \vdots & & \\
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176 \end{tabular}
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177 \caption{Stack layout on sparc64 calling convention}
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178 \end{figure}
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179