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annotate doc/manual/callconvs/callconv_sparc64.tex @ 330:4e6f63b7020e

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- stack layout typo for sparc doc
author Tassilo Philipp
date Fri, 22 Nov 2019 23:28:17 +0100
parents 276eb8c87aa0
children c9e19249ecd3
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1 %//////////////////////////////////////////////////////////////////////////////
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2 %
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3 % Copyright (c) 2012-2019 Daniel Adler <dadler@uni-goettingen.de>,
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4 % Tassilo Philipp <tphilipp@potion-studios.com>
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5 %
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6 % Permission to use, copy, modify, and distribute this software for any
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7 % purpose with or without fee is hereby granted, provided that the above
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8 % copyright notice and this permission notice appear in all copies.
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9 %
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10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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17 %
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18 %//////////////////////////////////////////////////////////////////////////////
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19
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20 \subsection{SPARC64 Calling Conventions}
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21
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22 \paragraph{Overview}
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23
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24 The SPARC family of processors is based on the SPARC instruction set architecture, which comes in basically three revisions,
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25 V7, V8\cite{SPARCV8}\cite{SPARCSysV} and V9\cite{SPARCV9}\cite{SPARCV9SysV}. The former two are 32-bit (see previous chapter) whereas the latter refers to the 64-bit SPARC architecture.
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26 SPARC uses big endian byte order, however, V9 supports also little endian byte order, but for data access only, not instruction access.\\
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27 \\
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28 There are two proposals, one from Sun and one from Hal, which disagree on how to handle some aspects of this calling convention.\\
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29
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30 \paragraph{\product{dyncall} support}
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31
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32 \product{dyncall} fully supports the SPARC 64-bit instruction set (V9), for calls and callbacks.
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33
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34 \subsubsection{SPARC (64-bit) Calling Convention}
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35
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36 \begin{itemize}
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37 \item 32 double precision floating point registers (d0,d2,d4,...,d62, usable as 16 quad precision ones q0,q4,q8,...g60, and also first half of them are usable as 32 single precision registers f0-f31)
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38 \item 32 64-bit integer/pointer registers out of a bigger (vendor/model dependent) number that are accessible at a time (8 are global ones (g*), whereas the remaining 24 form a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones)
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39 \item calling a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore)
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40 \item stack and frame pointer are offset by a BIAS of 2047 (see official doc for reasons)
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41 \end{itemize}
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42
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43 \begin{table}[h]
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44 \begin{tabular*}{0.95\textwidth}{lll}
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45 Name & Alias & Brief description\\
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46 \hline
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47 {\bf \%g0} & \%r0 & Read-only, hardwired to 0 \\
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48 {\bf \%g1-\%g7} & \%r1-\%r7 & Global \\
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49 {\bf \%o0-\%o3 and \%i0-\%i3} & \%r8-\%r11 and \%r24-\%r27 & Output and input argument registers, return value \\
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50 {\bf \%o4,\%o5 and \%i4,\%i5} & \%r12,\%r13 and \%r28,\%r29 & Output and input argument registers \\
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51 {\bf \%o6 and \%i6} & \%r14 and \%r30, \%sp and \%fp & Stack and frame pointer (NOTE, offset with a BIAS of 2047) \\
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52 {\bf \%o7 and \%i7} & \%r15 and \%r31 & Return address (caller writes to o7, callee uses i7) \\
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53 {\bf \%l0-\%l7} & \%r16-\%r23 & preserve \\
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54 {\bf \%d0,\%d2,\%d4,\%d6} & & scratch, Floating point arguments, return value \\
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55 {\bf \%d8,\%d10,...,\%d14} & & scratch, Floating point arguments \\
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56 {\bf \%d16,\%d18,...,\%d30} & & scratch (preserve for Hal), Floating point arguments \\
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57 {\bf \%d32,\%d34,...,\%d62} & & scratch (preserve for Hal) \\
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58 \end{tabular*}
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59 \caption{Register usage on sparc64 calling convention}
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60 \end{table}
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61
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62 \paragraph{Parameter passing}
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63 \begin{itemize}
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64 \item stack grows down
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65 \item stack parameter order: right-to-left
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66 \item caller cleans up the stack
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67 \item stack frame is always aligned to 16 bytes
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68 \item first 6 integers are passed in registers using \%o0-\%o5
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69 \item first 8 quad precision floating point args (or 16 double precision, or 32 single precision) are passed in floating point registers (\%q0,\%q4,...,\%q28 or \%d0,\%d2,...,\%d30 or \%f0-\%f31, respectively)
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70 \item for every other argument the stack is used
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71 \item single precision floating point args are passed in odd \%f* registers, and are "right aligned" in their 8-byte space on the stack
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72 \item for every argument passed, corresponding \%o*, \%f* register or stack space is skipped (e.g. passing a double as 3rd call argument, \%d4 is used and \%o2 is skipped)
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73 \item all arguments \textless=\ 64 bit are passed as 64 bit values
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74 \item minimum stack size is 128 bytes, b/c stack pointer must always point at enough space to store all \%i* and \%l* registers, used when running out of register windows
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75 \item if needed, register spill area (both, integer and float arguments are spilled in order) is adjacent to parameters
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76 \end{itemize}
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77
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78 \paragraph{Return values}
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79
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80 \begin{itemize}
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81 \item results are expected by caller to be returned in \%o0-\%o3 (after reg window restore, meaning callee writes to \%i0-\%i3) for integers
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82 \item \%d0,\%d2,\%d4,\%d6 are used for floating point values
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83 \item the fields of structs/unions up to 32b are returned via the respective registers mentioned in the previous bullet points
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84 \item structs/unions \textgreater= 32b are returned in a space allocated by the caller, with a pointer to it passed as first parameter to the function called (meaning in \%o0)
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85 \end{itemize}
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86
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87 \paragraph{Stack layout}
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88
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89 % verified/amended: TP nov 2019 (see also doc/disas_examples/sparc64.sparc64.disas)
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90 Stack directly after function prolog:\\
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91
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92 \begin{figure}[h]
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93 \begin{tabular}{5|3|1 1}
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94 & \vdots & & \\
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95 \hhline{~=~~}
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96 local data (and padding) & \hspace{4cm} & & \mrrbrace{8}{caller's frame} \\
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97 \hhline{~-~~}
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98 \mrlbrace{6}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\
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99 & \ldots & & \\
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100 & arg 6 & & \\
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101 & \%o5 & \mrrbrace{3}{spill area} & \\
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102 & \ldots & & \\
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103 & \%o0 & & \\
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104 \hhline{~-~~}
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105 register save area (\%i* and \%l*) & & & \\
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106 \hhline{~=~~}
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107 local data (and padding) & & & \mrrbrace{3}{current frame} \\
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108 \hhline{~-~~}
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109 parameter area & & & \\
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110 \hhline{~-~~}
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111 & \vdots & & \\
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112 \end{tabular}
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113 \caption{Stack layout on sparc64 calling convention}
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114 \end{figure}
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115