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annotate doc/manual/callconvs/callconv_mips64.tex @ 499:fc614cb865c6
- doc and disasexample additions specific to non-trivial C++ aggregates as return values (incl. fixes to doc and additional LSB specific PPC32 section)
author | Tassilo Philipp |
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date | Mon, 04 Apr 2022 15:50:52 +0200 |
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1 %////////////////////////////////////////////////////////////////////////////// |
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2 % |
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3 % Copyright (c) 2007-2022 Daniel Adler <dadler@uni-goettingen.de>, |
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4 % Tassilo Philipp <tphilipp@potion-studios.com> |
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5 % |
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6 % Permission to use, copy, modify, and distribute this software for any |
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7 % purpose with or without fee is hereby granted, provided that the above |
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8 % copyright notice and this permission notice appear in all copies. |
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9 % |
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10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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17 % |
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18 %////////////////////////////////////////////////////////////////////////////// |
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19 |
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20 \subsection{MIPS64 Calling Conventions} |
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21 |
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22 \paragraph{Overview} |
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23 |
336 | 24 There are two main ABIs in use for MIPS64 chips, \emph{N64}\cite{MIPSn32/n64} |
25 and \emph{N32}\cite{MIPSn32/n64}. Both are basically the same, except that N32 | |
26 uses ILP32 as programming model (32-bit pointers and long integers), whereas | |
27 N64 uses LP64 (64-bit pointers and long integers). All registers of a MIPS64 | |
28 chip are considered to be 64-bit wide, even for the N32 calling convention.\\ | |
29 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due | |
30 to historical reasons (terminology didn't change from MIPS32).\\ | |
31 Other than that there are correspoding 64-bit versions other MIPS32 ABIs, e.g. | |
32 the EABI\cite{MIPSeabi} and O64\cite{MIPSo64}. | |
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33 |
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34 \paragraph{\product{dyncall} support} |
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35 |
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36 For MIPS 64-bit machines, dyncall supports the N64 calling conventions for calls and callbacks (for all four combinations of big/little-endian, and soft/hard-float targets). |
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37 The N32 calling convention might work - it used to, but hasn't been tested, recently. |
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38 |
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39 \subsubsection{MIPS N64 Calling Convention} |
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40 |
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41 \paragraph{Register usage} |
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42 |
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43 \begin{table}[h] |
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44 \begin{tabular*}{0.95\textwidth}{lll} |
336 | 45 Name & Alias & Brief description\\ |
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46 \hline |
336 | 47 {\bf \$0} & {\bf \$zero} & hardware zero \\ |
48 {\bf \$1} & {\bf \$at} & assembler temporary, scratch \\ | |
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49 {\bf \$2-\$3} & {\bf \$v0-\$v1} & return value (only integers on hard-float targets), scratch \\ |
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50 {\bf \$4-\$11} & {\bf \$a0-\$a7} & first arguments (only integers on hard-float targets), scratch \\ |
336 | 51 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & temporaries, scratch \\ |
52 {\bf \$25} & {\bf \$t9} & temporary, address callee for all PIC calls (by convention), scratch \\ | |
53 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserve \\ | |
54 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & reserved for kernel \\ | |
55 {\bf \$28} & {\bf \$gp} & global pointer, preserve \\ | |
56 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\ | |
57 {\bf \$30} & {\bf \$s8} & frame pointer, preserve \\ | |
58 {\bf \$31} & {\bf \$ra} & return address, preserve \\ | |
59 {\bf hi, lo} & & multiply/divide special registers \\ | |
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60 {\bf \$f0,\$f2} & & only on hard-float targets: float return values, scratch \\ |
336 | 61 {\bf \$f1,\$f3,\$f4-\$f11} & & only on hard-float targets: float temporaries, scratch \\ |
62 {\bf \$f12-\$f19} & & only on hard-float targets: float arguments, scratch \\ | |
63 {\bf \$f20-\$f23} & & only on hard-float targets: float temporaries, scratch \\ | |
64 {\bf \$f24-\$f31} & & only on hard-float targets: preserved \\ | |
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65 \end{tabular*} |
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66 \caption{Register usage on MIPS N64 calling convention} |
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67 \end{table} |
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68 |
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69 \paragraph{Parameter passing} |
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70 |
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71 \begin{itemize} |
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72 \item Stack grows down |
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73 \item Stack parameter order: right-to-left |
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74 \item Caller cleans up the stack |
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75 \item generally, first 8 params \textgreater=\ 64-bit are passed via registers |
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76 \item for hard-float targets: register arguments are passed via \$a0-\$a7 for integers and \$f12-\$f19 for floats - with mixed float and int parameters, some registers are left out (e.g. first parameter ends up in \$a0 or \$f12, second in \$a1 or \$f13, etc.) |
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77 \item for soft-float targets: register arguments are passed via \$a0-\$a7 |
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78 \item subsequent arguments are pushed onto the stack |
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79 \item all stack entries are 64-bit aligned |
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80 \item all stack regions are 16-byte aligned |
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81 \item if the callee takes the address of one of the parameters and uses it to address other unnamed parameters (e.g. varargs) it has to copy - in its prolog - the the argument registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed integer parameters require saving, though) % @@@ seems to *ONLY* spill with varargs, never for any other reason |
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82 \item float arguments passed in the variable part of a vararg call are passed like integers, meaning float registers don't ever need to be saved that way, so only \$a0-\$a7 are need to be spilled |
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83 \item quad precision float arguments are passed in even-odd register pairs, skipping one register if needed |
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84 \item integer parameters \textless\ 64 bit are right-justified (meaning occupy higher-address bytes) in their 8-byte slot on the stack, requiring extra-care for big-endian targets |
336 | 85 \item single precision float parameters (32 bit) are left-justified in their 8-byte slot on the stack, but are right justified in fp-registers on big endian targets, as they aren't promoted (actually, official docs says "undecided", but real world implementations seem to use what is described here) |
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86 \item aggregates (struct, union) are passed as a sequence of dwords in (integer registers and the stack), with the following particularities: |
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87 \item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate |
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88 \begin{itemize} |
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89 \item if a dword happens to be a double precision floating point struct field, it is passed in a floating point register |
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90 \item array and union fields are always passed like integers (even if their type is float or double) |
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91 \item splitting an argument across registers and the stack is fine |
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92 \end{itemize} |
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93 %spec |
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94 %Structs, unions, or other composite types are treated as a sequence of doublewords, |
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95 %and are passed in integer or floating point registers as though they were simple |
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96 %scalar parameters to the extent that they fit, with any excess on the stack packed |
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97 %according to the normal memory layout of the object. More specifically: |
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98 %- Regardless of the struct field structure, it is treated as a sequence of 64-bit |
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99 %chunks. If a chunk consists solely of a double float field (but not a double, |
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100 %which is part of a union), it is passed in a floating point register. Any other |
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101 %chunk is passed in an integer register. |
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102 %- A union, either as the parameter itself or as a struct parameter field, is treated |
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103 %as a sequence of integer doublewords for purposes of assignment to integer |
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104 %parameter registers. No attempt is made to identify floating point components |
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105 %for passing in floating point registers. |
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106 %- Array fields of structs are passed like unions. Array parameters are passed by |
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107 %reference (unless the relevant language standard requires otherwise). |
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108 %- Right-justifying small scalar parameters in their save area slots |
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109 %notwithstanding, struct parameters are always left-justified. This applies both |
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110 %to the case of a struct smaller than 64 bits, and to the final chunk of a struct |
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111 %which is not an integral multiple of 64 bits in size. The implication of this rule is |
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112 %that the address of the first chunk’s save area slot is the address of the struct, |
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113 %and the struct is laid out in the save area memory exactly as if it were allocated |
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114 %normally (once any part in registers has been stored to the save area). [These |
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115 %rules are analogous to the o32-bit ABI treatment – only the chunk size and the |
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116 %ability to pass double fields in floating point registers are different. |
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117 \end{itemize} |
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118 % maybe note somewhere that "prolog-based" spilling is neat for dyncall, as we don't have to care |
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119 |
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120 |
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121 \paragraph{Return values} |
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122 |
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123 \begin{itemize} |
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124 \item results are returned in \$v0, and for a second one \$v1 is used |
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125 \item only on hard-float targets: floating point results are returned in \$f0 (and \$f2 if needed) |
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126 \item only on hard-float targets: structs with only one or two floating point fields are returned in \$f0 (and \$f2 if necessary), field-by-field |
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127 \item for {\it non-trivial} C++ aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param |
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128 (meaning in \%a0), and callee writes return value to this space; the ptr to the aggregate is returned in \%v0 |
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129 \item any other aggregates (struct, union) \textless= 16 bytes are returned via registers \$v0 (and \$v1 if necessary), dword-by-dword |
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130 \item all other aggregates (struct, union) \textgreater 16 bytes are returned in a space allocated by the caller, with a pointer to it |
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131 passed as first parameter to the function called (meaning in \%a0); the ptr to the aggregate is returned in \%v0 |
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132 %spec; |
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133 %Composite results (struct, union, or array) are returned in |
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134 %$2/$f0 and $3/$f2 according to the following rules: |
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135 %- A struct with only one or two floating point fields is returned in $f0 (and $f2 if |
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136 %necessary). This is a generalization of the Fortran COMPLEX case. |
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137 %- Any other struct or union results of at most 128 bits are returned in $2 (first 64 |
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138 %bits) and $3 (remainder, if necessary). |
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139 %- Larger composite results are handled by converting the function to a procedure |
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140 %with an implicit first parameter, which is a pointer to an area reserved by the |
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141 %caller to receive the result. [The o32-bit ABI requires that all composite results |
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142 %be handled by conversion to implicit first parameters. The MIPS/SGI Fortran |
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143 %implementation has always made a specific exception to return COMPLEX |
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144 %results in the floating point registers.] |
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145 \end{itemize} |
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146 |
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147 |
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148 \paragraph{Stack layout} |
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149 |
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150 % verified/amended: TP nov 2019 (see also doc/disas_examples/mips64.n64.disas) |
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151 Stack directly after function prolog:\\ |
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152 |
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153 \begin{figure}[h] |
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154 \begin{tabular}{5|3|1 1} |
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155 & \vdots & & \\ |
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156 \hhline{~=~~} |
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157 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ |
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158 \hhline{~-~~} |
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159 local data & & & \\ |
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160 \hhline{~-~~} |
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161 \mrlbrace{6}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\ |
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162 & \ldots & & \\ |
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163 & arg 8 & & \\ |
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164 \hhline{~=~~} |
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165 & \$a7 & \mrrbrace{3}{spill area (if needed)} & \mrrbrace{6}{current frame} \\ |
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166 & \ldots & & \\ |
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167 & \$a? (first unnamed reg) & & \\ |
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168 \hhline{~-~~} |
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169 register save area (with return address) & & & \\ |
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170 \hhline{~-~~} |
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171 local data & & & \\ |
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172 \hhline{~-~~} |
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173 parameter area & \vdots & & \\ |
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174 \end{tabular} |
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175 \caption{Stack layout on MIPS N64 calling convention} |
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176 \end{figure} |
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177 |
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178 |
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179 \subsubsection{MIPS N32 Calling Convention} |
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180 |
336 | 181 Despite what one might think given the name, this is a MIPS 64-bit calling |
182 convention. As mentioned in the overview of this chapter, it is nearly | |
183 identical to the N64 one, the differences being: | |
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184 |
336 | 185 \begin{itemize} |
186 \item uses ILP32 as programming model instead of LP64 | |
187 \item floating point registers \$f20-\$f23 are to be preserved | |
188 \end{itemize} | |
189 |