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- review and fixes, cleanup, amendments to calling convention appendix of manual
author Tassilo Philipp
date Fri, 22 Nov 2019 23:11:56 +0100
parents b104c5beec8b
children 3c6bc720bc1f
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1 %//////////////////////////////////////////////////////////////////////////////
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2 %
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3 % Copyright (c) 2007-2019 Daniel Adler <dadler@uni-goettingen.de>,
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4 % Tassilo Philipp <tphilipp@potion-studios.com>
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5 %
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6 % Permission to use, copy, modify, and distribute this software for any
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7 % purpose with or without fee is hereby granted, provided that the above
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8 % copyright notice and this permission notice appear in all copies.
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9 %
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10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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17 %
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18 %//////////////////////////////////////////////////////////////////////////////
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19
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20 \subsection{MIPS64 Calling Conventions}
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21
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22 \paragraph{Overview}
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23
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24 There are two main ABIs in use for MIPS64 chips, \emph{N64}\cite{MIPSn32/n64} and \emph{N32}\cite{MIPSn32/n64}. Both are
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25 basically the same, except that N32 uses 32-bit pointers and long integers, instead of 64. All registers of a MIPS64 chip are considered
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26 to be 64-bit wide, even for the N32 calling convention.\\
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27 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due to historical reasons (terminology didn't change from MIPS32).\\
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28 Other than that there are correspoding 64-bit versions other MIPS32 ABIs, e.g. the EABI\cite{MIPSeabi} and O64\cite{MIPSo64}.
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29
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30 \paragraph{\product{dyncall} support}
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31
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32 For MIPS 64-bit machines, dyncall supports the N64 calling conventions for calls and callbacks (for all four combinations of big/little-endian, and soft/hard-float targets).
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33 The N32 calling convention might work - it used to, but hasn't been tested, recently.
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34
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35 \subsubsection{MIPS N64 Calling Convention}
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36
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37 \paragraph{Register usage}
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38
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39 \begin{table}[h]
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40 \begin{tabular*}{0.95\textwidth}{lll}
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41 Name & Alias & Brief description\\
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42 \hline
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43 {\bf \$0} & {\bf \$zero} & hardware zero \\
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44 {\bf \$1} & {\bf \$at} & assembler temporary, scratch \\
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45 {\bf \$2-\$3} & {\bf \$v0-\$v1} & return value (only integer on hard-float targets), scratch \\
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46 {\bf \$4-\$11} & {\bf \$a0-\$a7} & first arguments (only integer on hard-float targets), scratch \\
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47 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & temporaries, scratch \\
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48 {\bf \$25} & {\bf \$t9} & temporary, address callee for all PIC calls (by convention), scratch \\
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49 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserve \\
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50 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & reserved for kernel \\
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51 {\bf \$28} & {\bf \$gp} & global pointer, preserve \\
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52 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\
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53 {\bf \$30} & {\bf \$s8} & frame pointer, preserve \\
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54 {\bf \$31} & {\bf \$ra} & return address, preserve \\
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55 {\bf hi, lo} & & multiply/divide special registers \\
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56 {\bf \$f0,\$f2} & & only on hard-float targets: float results, scratch \\
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57 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & only on hard-float targets: float temporaries, scratch \\
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58 {\bf \$f12-\$f19} & & only on hard-float targets: float arguments, scratch \\
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59 {\bf \$f24-\$f31} & & only on hard-float targets: preserved \\%@@@on N32, this changes
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60 \end{tabular*}
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61 \caption{Register usage on MIPS N64 calling convention}
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62 \end{table}
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63
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64 \paragraph{Parameter passing}
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65
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66 \begin{itemize}
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67 \item Stack grows down
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68 \item Stack parameter order: right-to-left
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69 \item Caller cleans up the stack
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70 \item generally, first 8 params \textgreater=\ 64-bit are passed via registers
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71 \item for hard-float targets: register arguments are passed via \$a0-\$a7 for integers and \$f12-\$f19 for floats - with mixed float and int parameters, some registers are left out (e.g. first parameter ends up in \$a0 or \$f12, second in \$a1 or \$f13, etc.)
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72 \item for soft-float targets: register arguments are passed via \$a0-\$a7
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73 \item subsequent arguments are pushed onto the stack
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74 \item all stack entries are 64-bit aligned
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75 \item all stack regions are 16-byte aligned
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76 \item results are returned in \$v0, and for a second one \$v1 is used
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77 \item only on hard-float targets: floating point results are returned in \$f0
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78 \item if the callee takes the address of one of the parameters and uses it to address other unnamed parameters (e.g. varargs) it has to copy - in its prolog - the the argument registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed integer parameters require saving, though) % @@@ seems to *ONLY* spill with varargs, never for any other reason
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79 \item float arguments passed in the variable part of a vararg call are passed like integers, meaning float registers don't ever need to be saved that way, so only \$a0-\$a7 are need to be spilled
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80 \item quad precision float arguments are passed in even-odd register pairs, skipping one register if needed
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81 \item integer parameters \textless\ 64 bit are right-justified (meaning occupy higher-address bytes) in their 8-byte slot on the stack, requiring extra-care for big-endian targets
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82 \item single precision float parameters (32 bit) are left-justified in their 8-byte slot on the stack, but are right justified in fp-registers on big endian targets, as they aren't promoted @@@doc says "undecided", but openbsd/octeon(mipseb) has it as described here
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83 \end{itemize}
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84 % maybe note somewhere that "prolog-based" spilling is neat for dyncall, as we don't have to care
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85
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86 \paragraph{Stack layout}
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87
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88 % verified/amended: TP nov 2019 (see also doc/disas_examples/mips64.n64.disas)
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89 Stack directly after function prolog:\\
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90
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91 \begin{figure}[h]
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92 \begin{tabular}{5|3|1 1}
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93 & \vdots & & \\
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94 \hhline{~=~~}
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95 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\
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96 \hhline{~-~~}
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97 local data & & & \\
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98 \hhline{~-~~}
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99 \mrlbrace{6}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\
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100 & \ldots & & \\
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101 & arg 8 & & \\
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102 \hhline{~=~~}
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103 & \$a7 & \mrrbrace{3}{spill area (if needed)} & \mrrbrace{6}{current frame} \\
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104 & \ldots & & \\
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105 & \$a? (first unnamed reg) & & \\
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106 \hhline{~-~~}
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107 register save area (with return address) & & & \\
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108 \hhline{~-~~}
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109 local data & & & \\
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110 \hhline{~-~~}
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111 parameter area & \vdots & & \\
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112 \end{tabular}
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113 \caption{Stack layout on MIPS N64 calling convention}
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114 \end{figure}
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115
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116
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117 \subsubsection{MIPS N32 Calling Convention}
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118
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119 @@@
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120