Mercurial > pub > dyncall > dyncall
annotate doc/manual/callconvs/callconv_mips64.tex @ 302:d55f9d508074
- mips softfloat support for o32 callconv (calls and callbacks, little and big endian)
- cleanup of some mips files, removed unnecessary file, renamings..
- doc/manual cleanups, changelog entry
| author | Tassilo Philipp |
|---|---|
| date | Mon, 21 May 2018 02:48:12 +0200 |
| parents | e210193f6cf1 |
| children | b104c5beec8b |
| rev | line source |
|---|---|
| 0 | 1 %////////////////////////////////////////////////////////////////////////////// |
| 2 % | |
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3 % Copyright (c) 2007-2016 Daniel Adler <dadler@uni-goettingen.de>, |
| 0 | 4 % Tassilo Philipp <tphilipp@potion-studios.com> |
| 5 % | |
| 6 % Permission to use, copy, modify, and distribute this software for any | |
| 7 % purpose with or without fee is hereby granted, provided that the above | |
| 8 % copyright notice and this permission notice appear in all copies. | |
| 9 % | |
| 10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| 11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| 12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| 13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| 14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| 15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| 16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| 17 % | |
| 18 %////////////////////////////////////////////////////////////////////////////// | |
| 19 | |
| 20 \subsection{MIPS64 Calling Convention} | |
| 21 | |
| 22 \paragraph{Overview} | |
| 23 | |
| 117 | 24 There are two main ABIs in use for MIPS64 chips, \emph{N64}\cite{MIPSn32/n64} and \emph{N32}\cite{MIPSn32/n64}. Both are |
| 25 basically the same, except that N32 uses 32-bit pointers and long integers, instead of 64. All registers of a MIPS64 chip are considered | |
| 26 to be 64-bit wide, even for the N32 calling convention.\\ | |
| 27 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due to historical reasons (terminology didn't change from MIPS32).\\ | |
| 28 Other than that there are 64-bit versions of the other ABIs found for MIPS32, e.g. the EABI\cite{MIPSeabi} and O64\cite{MIPSo64}. | |
| 0 | 29 |
| 30 \paragraph{\product{dyncall} support} | |
| 31 | |
| 139 | 32 For MIPS 64-bit machines, dyncall supports the N64 calling conventions for calls and callbacks (for big- and little-endian targets). |
| 33 The N32 calling convention might work - it used to, but hasn't been tested, recently. | |
| 117 | 34 |
| 35 \subsubsection{MIPS N64 Calling Convention} | |
| 36 | |
| 37 \paragraph{Register usage} | |
| 38 | |
| 39 \begin{table}[h] | |
| 40 \begin{tabular*}{0.95\textwidth}{lll} | |
| 41 Name & Alias & Brief description\\ | |
| 42 \hline | |
| 43 {\bf \$0} & {\bf \$zero} & Hardware zero \\ | |
| 44 {\bf \$1} & {\bf \$at} & Assembler temporary \\ | |
| 45 {\bf \$2-\$3} & {\bf \$v0-\$v1} & Integer results \\ | |
| 46 {\bf \$4-\$11} & {\bf \$a0-\$a7} & Integer arguments, or double precision float arguments\\ | |
| 47 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & Integer temporaries \\ | |
| 48 {\bf \$25} & {\bf \$t9} & Integer temporary, hold the address of the called function for all PIC calls (by convention) \\ | |
| 49 {\bf \$16-\$23} & {\bf \$s0-\$s7} & Preserved \\ | |
| 50 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & Reserved for kernel \\ | |
| 51 {\bf \$28} & {\bf \$gp} & Global pointer, preserve \\ | |
| 52 {\bf \$29} & {\bf \$sp} & Stack pointer, preserve \\ | |
| 53 {\bf \$30} & {\bf \$s8} & Frame pointer, preserve \\ | |
| 54 {\bf \$31} & {\bf \$ra} & Return address, preserve \\ | |
| 55 {\bf hi, lo} & & Multiply/divide special registers \\ | |
| 56 {\bf \$f0,\$f2} & & Float results \\ | |
| 57 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & Float temporaries \\ | |
| 58 {\bf \$f12-\$f19} & & Float arguments \\ | |
| 59 {\bf \$f24-\$f31} & & Preserved \\%@@@on N32, this changes | |
| 60 \end{tabular*} | |
| 61 \caption{Register usage on MIPS N64 calling convention} | |
| 62 \end{table} | |
| 63 | |
| 64 \paragraph{Parameter passing} | |
| 0 | 65 |
| 117 | 66 \begin{itemize} |
| 67 \item Stack grows down | |
| 68 \item Stack parameter order: right-to-left | |
| 69 \item Caller cleans up the stack | |
| 119 | 70 \item first 8 params \textgreater=\ 64-bit are passed in registers \$a0-\$a7 for integers and \$f12-\$f19 for floats - with mixed float and int parameters, |
| 71 some registers are left out (e.g. first parameter ends up in \$a0 or \$f12, second in \$a1 or \$f13, etc.) | |
| 72 \item subsequent arguments are pushed onto the stack | |
| 117 | 73 \item all stack entries are 64-bit aligned |
| 119 | 74 \item all stack regions are 16-byte aligned |
| 117 | 75 \item results are returned in \$v0, and for a second one \$v1 is used |
| 76 \item float arguments passed in the variable part of a vararg call are passed like integers | |
| 125 | 77 \item quad precision float arguments are passed in even-odd register pairs, skipping one register if needed |
| 78 \item integer parameters \textless\ 64 bit are right-justified (meaning occupy higher-address bytes) in their 8-byte slot on the stack, requiring extra-care for big-endian targets | |
| 79 \item single precision float parameters (32 bit) are left-justified in their 8-byte slot on the stack, but are right justified in fp-registers on big endian targets, as they aren't promoted @@@doc says "undecided", but openbsd/octeon(mipseb) has it as described here | |
| 117 | 80 \end{itemize} |
| 0 | 81 |
| 117 | 82 \paragraph{Stack layout} |
| 0 | 83 |
| 117 | 84 Stack directly after function prolog:\\ |
| 119 | 85 @@@ WIP, might be wrong |
| 117 | 86 |
| 87 \begin{figure}[h] | |
| 88 \begin{tabular}{5|3|1 1} | |
| 89 \hhline{~-~~} | |
| 90 & \vdots & & \\ | |
| 91 \hhline{~=~~} | |
| 92 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ | |
| 93 \hhline{~-~~} | |
| 94 local data & & & \\ | |
| 95 \hhline{~-~~} | |
| 96 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ | |
| 97 & \ldots & & \\ | |
| 98 & \ldots & & \\ | |
| 99 \hhline{~=~~} | |
| 119 | 100 register save area & padding & & \mrrbrace{7}{current frame} \\ |
| 117 | 101 & \$ra & & \\ |
| 102 & \$s8 & & \\ | |
| 103 & \$gp & & \\ | |
| 104 \hhline{~-~~} | |
| 105 local data & & & \\ | |
| 106 \hhline{~-~~} | |
| 107 parameter area & & & \\ | |
| 108 \hhline{~-~~} | |
| 109 & \vdots & & \\ | |
| 110 \hhline{~-~~} | |
| 111 \end{tabular} | |
| 112 \caption{Stack layout on mips64 n64 calling convention} | |
| 113 \end{figure} | |
| 114 | |
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- mips softfloat support for o32 callconv (calls and callbacks, little and big endian)
Tassilo Philipp
parents:
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115 |
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d55f9d508074
- mips softfloat support for o32 callconv (calls and callbacks, little and big endian)
Tassilo Philipp
parents:
186
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116 \subsubsection{MIPS N32 Calling Convention} |
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d55f9d508074
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Tassilo Philipp
parents:
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117 |
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d55f9d508074
- mips softfloat support for o32 callconv (calls and callbacks, little and big endian)
Tassilo Philipp
parents:
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118 @@@ |
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d55f9d508074
- mips softfloat support for o32 callconv (calls and callbacks, little and big endian)
Tassilo Philipp
parents:
186
diff
changeset
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119 |