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- review and fixes, cleanup, amendments to calling convention appendix of manual
author Tassilo Philipp
date Fri, 22 Nov 2019 23:11:56 +0100
parents e07fb0bbddae
children 4e6f63b7020e
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1 %//////////////////////////////////////////////////////////////////////////////
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2 %
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3 % Copyright (c) 2012-2019 Daniel Adler <dadler@uni-goettingen.de>,
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4 % Tassilo Philipp <tphilipp@potion-studios.com>
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5 %
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6 % Permission to use, copy, modify, and distribute this software for any
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7 % purpose with or without fee is hereby granted, provided that the above
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8 % copyright notice and this permission notice appear in all copies.
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9 %
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10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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17 %
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18 %//////////////////////////////////////////////////////////////////////////////
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19
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20 \subsection{SPARC Calling Conventions}
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21
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22 \paragraph{Overview}
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23
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24 The SPARC family of processors is based on the SPARC instruction set architecture, which comes in basically three revisions,
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25 V7, V8\cite{SPARCV8}\cite{SPARCSysV} and V9\cite{SPARCV9}\cite{SPARCV9SysV}. The former two are 32-bit whereas the latter refers to the 64-bit SPARC architecture (see next chapter).
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26 SPARC uses big endian byte order.\\
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27 The word size is defined to be 32 bits.
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28
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29 \paragraph{\product{dyncall} support}
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30
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31 \product{dyncall} fully supports the SPARC 32-bit instruction set (V7 and V8), for calls and callbacks.
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32
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33 \subsubsection{SPARC (32-bit) Calling Convention}
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34
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35 \paragraph{Register usage}
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36
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37 \begin{itemize}
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38 \item 32 single floating point registers (f0-f31, usable as 8 quad precision q0,q4,q8,...,q28, 16 double precision d0,d2,d4,...,d30)
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39 \item 32 32-bit integer/pointer registers out of a bigger (vendor/model dependent) number that are accessible at a time (8 are global ones (g*), whereas the remaining 24 form a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones)
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40 \item calling a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore)
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41 \end{itemize}
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42
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43 \begin{table}[h]
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44 \begin{tabular*}{0.95\textwidth}{lll}
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45 Name & Alias & Brief description\\
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46 \hline
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47 {\bf \%g0} & \%r0 & Read-only, hardwired to 0 \\
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48 {\bf \%g1-\%g7} & \%r1-\%r7 & Global \\
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49 {\bf \%o0,\%o1 and \%i0,\%i1} & \%r8,\%r9 and \%r24,\%r25 & Output and input argument registers, return value \\
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50 {\bf \%o2-\%o5 and \%i2-\%i5} & \%r10-\%r13 and \%r26-\%r29 & Output and input argument registers \\
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51 {\bf \%o6 and \%i6} & \%r14 and \%r30, \%sp and \%fp & Stack and frame pointer \\
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52 {\bf \%o7 and \%i7} & \%r15 and \%r31 & Return address (caller writes to o7, callee uses i7) \\
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53 {\bf \%l0-\%l7} & \%r16-\%r23 & preserve \\
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54 {\bf \%f0,\%f1} & & Floating point return value \\
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55 {\bf \%f2-\%f31} & & scratch \\
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56 \end{tabular*}
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57 \caption{Register usage on sparc calling convention}
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58 \end{table}
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59
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60 \paragraph{Parameter passing}
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61 \begin{itemize}
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62 \item stack grows down
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63 \item stack parameter order: right-to-left
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64 \item caller cleans up the stack
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65 \item stack always aligned to 8 bytes
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66 \item first 6 integers and floats are passed independently in registers using \%o0-\%o5
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67 \item for every other argument the stack is used
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68 \item all arguments \textless=\ 32 bit are passed as 32 bit values
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69 \item 64 bit arguments are passed like two consecutive \textless=\ 32 bit values (which allows for an argument to be split between the stack and \%i5)
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70 \item minimum stack size is 64 bytes, b/c stack pointer must always point at enough space to store all \%i* and \%l* registers, used when running out of register windows
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71 \item if needed, register spill area is adjacent to parameters
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72 \end{itemize}
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73
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74 \paragraph{Return values}
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75
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76 \begin{itemize}
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77 \item results are expected by caller to be returned in \%o0/\%o1 (after reg window restore, meaning callee writes to \%i0/\%i1) for integers
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78 \item \%f0/\%f1 are used for floating point values
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79 \item structs/unions are returned in a space allocated by the caller, with a pointer to it passed as a {\bf additional}, hidden stack parameter (see below)
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80 \end{itemize}
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81
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82 \paragraph{Stack layout}
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83
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84 % verified/amended: TP nov 2019 (see also doc/disas_examples/sparc.sparc.disas)
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85 Stack directly after function prolog:\\
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86
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87 \begin{figure}[h]
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88 \begin{tabular}{5|3|1 1}
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89 & \vdots & & \\
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90 \hhline{~=~~}
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91 local data (and padding) & \hspace{4cm} & & \mrrbrace{9}{caller's frame} \\
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92 \hhline{~-~~}
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93 \mrlbrace{7}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\
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94 & \ldots & & \\
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95 & 7th word of arg data & & \\
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96 & \%5 & \mrrbrace{3}{spill area} & \\
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97 & \ldots & & \\
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98 & \%0 & & \\
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99 & struct/union return pointer & & \\
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100 \hhline{~-~~}
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101 register save area (\%i* and \%l*) & & & \\
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102 \hhline{~=~~}
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103 local data (and padding) & & & \mrrbrace{3}{current frame} \\
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104 \hhline{~-~~}
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105 parameter area & & & \\
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106 \hhline{~-~~}
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107 & \vdots & & \\
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108 \end{tabular}
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109 \caption{Stack layout on sparc32 calling convention}
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110 \end{figure}
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111