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diff doc/manual/callconvs/callconv_arm32.tex @ 486:d160046da104

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doc cleanup: removed outdated/wrong info and fixed wrong value size specs
author Tassilo Philipp
date Thu, 17 Mar 2022 17:56:44 +0100
parents 0fc22b5feac7
children 75cb8f79d725
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--- a/doc/manual/callconvs/callconv_arm32.tex	Thu Mar 17 15:41:26 2022 +0100
+++ b/doc/manual/callconvs/callconv_arm32.tex	Thu Mar 17 17:56:44 2022 +0100
@@ -142,12 +142,6 @@
 
 \paragraph{Status}
 
-\begin{itemize}
-\item The ATPCS THUMB mode is untested.
-\item Ellipsis calls may not work.
-\item C++ this calls do not work.
-\end{itemize}
-
 \paragraph{Registers and register usage}
 
 In THUMB mode, the ARM32 processor family supports eight 32 bit general purpose registers r0-r7 and access to high order registers r8-r15:\\