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comparison doc/manual/callconvs/callconv_arm32.tex @ 76:7ca46969e0ad

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- tweaks in manual, mainly for html generation
author cslag
date Mon, 21 Mar 2016 01:15:37 +0100
parents 9e9d6a90492a
children e441ef3ec782
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75:a59ae4370202 76:7ca46969e0ad
25 The ARM32 family of processors is based on 25 The ARM32 family of processors is based on
26 the Advanced RISC Machines (ARM) processor architecture (32 bit RISC). 26 the Advanced RISC Machines (ARM) processor architecture (32 bit RISC).
27 The word size is 32 bits (and the programming model is LLP64).\\ 27 The word size is 32 bits (and the programming model is LLP64).\\
28 Basically, this family of microprocessors can be run in 2 major modes:\\ 28 Basically, this family of microprocessors can be run in 2 major modes:\\
29 \\ 29 \\
30 \begin{tabular}{2 B} 30 \begin{tabular*}{0.75\textwidth}{2 B}
31 \hline 31 \hline
32 Mode & Description\\ 32 Mode & Description\\
33 \hline 33 \hline
34 {\bf ARM} & 32bit instruction set\\ 34 {\bf ARM} & 32bit instruction set\\
35 {\bf THUMB} & compressed instruction set using 16bit wide instruction encoding\\ 35 {\bf THUMB} & compressed instruction set using 16bit wide instruction encoding\\
36 \hline 36 \hline
37 \end{tabular} 37 \end{tabular*}
38 \\ 38 \\
39 \\ 39 \\
40 For more details, take a look at the ARM-THUMB Procedure Call Standard (ATPCS) \cite{ATPCS}, the Procedure Call Standard for the ARM Architecture (AAPCS) \cite{AAPCS}, as well as the Debian ARM EABI port wiki \cite{armeabi}. 40 For more details, take a look at the ARM-THUMB Procedure Call Standard (ATPCS) \cite{ATPCS}, the Procedure Call Standard for the ARM Architecture (AAPCS) \cite{AAPCS}, as well as the Debian ARM EABI port wiki \cite{armeabi}.
41 41
42 42
53 \paragraph{Registers and register usage} 53 \paragraph{Registers and register usage}
54 54
55 In ARM mode, the ARM32 processor has sixteen 32 bit general purpose registers, namely r0-r15:\\ 55 In ARM mode, the ARM32 processor has sixteen 32 bit general purpose registers, namely r0-r15:\\
56 \\ 56 \\
57 \begin{table}[h] 57 \begin{table}[h]
58 \begin{tabular}{3 B} 58 \begin{tabular*}{0.75\textwidth}{3 B}
59 \hline 59 \hline
60 Name & Brief description\\ 60 Name & Brief description\\
61 \hline 61 \hline
62 {\bf r0} & parameter 0, scratch, return value\\ 62 {\bf r0} & parameter 0, scratch, return value\\
63 {\bf r1} & parameter 1, scratch, return value\\ 63 {\bf r1} & parameter 1, scratch, return value\\
67 {\bf r12} & scratch\\ 67 {\bf r12} & scratch\\
68 {\bf r13} & stack pointer, permanent\\ 68 {\bf r13} & stack pointer, permanent\\
69 {\bf r14} & link register, permanent\\ 69 {\bf r14} & link register, permanent\\
70 {\bf r15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\ 70 {\bf r15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
71 \hline 71 \hline
72 \end{tabular} 72 \end{tabular*}
73 \caption{Register usage on arm32} 73 \caption{Register usage on arm32}
74 \end{table} 74 \end{table}
75 75
76 \paragraph{Parameter passing} 76 \paragraph{Parameter passing}
77 77
144 \paragraph{Registers and register usage} 144 \paragraph{Registers and register usage}
145 145
146 In THUMB mode, the ARM32 processor family supports eight 32 bit general purpose registers r0-r7 and access to high order registers r8-r15:\\ 146 In THUMB mode, the ARM32 processor family supports eight 32 bit general purpose registers r0-r7 and access to high order registers r8-r15:\\
147 \\ 147 \\
148 \begin{table}[h] 148 \begin{table}[h]
149 \begin{tabular}{3 B} 149 \begin{tabular*}{0.75\textwidth}{3 B}
150 \hline 150 \hline
151 Name & Brief description\\ 151 Name & Brief description\\
152 \hline 152 \hline
153 {\bf r0} & parameter 0, scratch, return value\\ 153 {\bf r0} & parameter 0, scratch, return value\\
154 {\bf r1} & parameter 1, scratch, return value\\ 154 {\bf r1} & parameter 1, scratch, return value\\
159 {\bf r12} & scratch\\ 159 {\bf r12} & scratch\\
160 {\bf r13} & stack pointer, permanent\\ 160 {\bf r13} & stack pointer, permanent\\
161 {\bf r14} & link register, permanent\\ 161 {\bf r14} & link register, permanent\\
162 {\bf r15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\ 162 {\bf r15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
163 \hline 163 \hline
164 \end{tabular} 164 \end{tabular*}
165 \caption{Register usage on arm32 thumb mode} 165 \caption{Register usage on arm32 thumb mode}
166 \end{table} 166 \end{table}
167 167
168 \paragraph{Parameter passing} 168 \paragraph{Parameter passing}
169 169
253 Typically code is compiled in Thumb mode. 253 Typically code is compiled in Thumb mode.
254 254
255 \paragraph{Register usage} 255 \paragraph{Register usage}
256 256
257 \begin{table}[h] 257 \begin{table}[h]
258 \begin{tabular}{3 B} 258 \begin{tabular*}{0.75\textwidth}{3 B}
259 \hline 259 \hline
260 Name & Brief description\\ 260 Name & Brief description\\
261 \hline 261 \hline
262 {\bf R0} & parameter 0, scratch, return value\\ 262 {\bf R0} & parameter 0, scratch, return value\\
263 {\bf R1} & parameter 1, scratch, return value\\ 263 {\bf R1} & parameter 1, scratch, return value\\
275 {\bf D0-D7} & scratch. aliases S0-S15, on ARMv7 also as Q0-Q3. Not accessible from Thumb mode on ARMv6.\\ 275 {\bf D0-D7} & scratch. aliases S0-S15, on ARMv7 also as Q0-Q3. Not accessible from Thumb mode on ARMv6.\\
276 {\bf D8-D15} & permanent, aliases S16-S31, on ARMv7 also as Q4-A7. Not accesible from Thumb mode on ARMv6.\\ 276 {\bf D8-D15} & permanent, aliases S16-S31, on ARMv7 also as Q4-A7. Not accesible from Thumb mode on ARMv6.\\
277 {\bf D16-D31}& Only available in ARMv7, aliases Q8-Q15.\\ 277 {\bf D16-D31}& Only available in ARMv7, aliases Q8-Q15.\\
278 {\bf FPSCR} & VFP status register.\\ 278 {\bf FPSCR} & VFP status register.\\
279 \hline 279 \hline
280 \end{tabular} 280 \end{tabular*}
281 \caption{Register usage on ARM Apple iOS} 281 \caption{Register usage on ARM Apple iOS}
282 \end{table} 282 \end{table}
283 283
284 The ABI is based on the AAPCS but with some important differences listed below: 284 The ABI is based on the AAPCS but with some important differences listed below:
285 285
299 Code is little-endian, rest is similar to EABI with an 8-byte aligned stack, etc.. 299 Code is little-endian, rest is similar to EABI with an 8-byte aligned stack, etc..
300 300
301 \paragraph{Register usage} 301 \paragraph{Register usage}
302 302
303 \begin{table}[h] 303 \begin{table}[h]
304 \begin{tabular}{3 B} 304 \begin{tabular*}{0.75\textwidth}{3 B}
305 \hline 305 \hline
306 Name & Brief description\\ 306 Name & Brief description\\
307 \hline 307 \hline
308 {\bf R0} & parameter 0, scratch, non floating point return value\\ 308 {\bf R0} & parameter 0, scratch, non floating point return value\\
309 {\bf R1} & parameter 1, scratch, non floating point return value\\ 309 {\bf R1} & parameter 1, scratch, non floating point return value\\
323 {\bf D0} & floating point argument, floating point return value, double precision, aliases S0-S1, \\ 323 {\bf D0} & floating point argument, floating point return value, double precision, aliases S0-S1, \\
324 {\bf S1-S15} & floating point arguments, single precision\\ 324 {\bf S1-S15} & floating point arguments, single precision\\
325 {\bf D1-D7} & aliases S2-S15, floating point arguments, double precision\\ 325 {\bf D1-D7} & aliases S2-S15, floating point arguments, double precision\\
326 {\bf FPSCR} & VFP status register.\\ 326 {\bf FPSCR} & VFP status register.\\
327 \hline 327 \hline
328 \end{tabular} 328 \end{tabular*}
329 \caption{Register usage on armhf} 329 \caption{Register usage on armhf}
330 \end{table} 330 \end{table}
331 331
332 \paragraph{Parameter passing} 332 \paragraph{Parameter passing}
333 333
370 % ARM 7: ARMv4T 370 % ARM 7: ARMv4T
371 % ARM 9: ARMv4T, HTC Wizard 371 % ARM 9: ARMv4T, HTC Wizard
372 % Cortex-*: ARMv7, Raspberry Pi 2, ... 372 % Cortex-*: ARMv7, Raspberry Pi 2, ...
373 373
374 \begin{table}[h] 374 \begin{table}[h]
375 \begin{tabular}{lll} 375 \begin{tabular*}{0.75\textwidth}{lll}
376 Arch & Platforms & Details \\ 376 Arch & Platforms & Details \\
377 \hline 377 \hline
378 ARMv4 & & \\ 378 ARMv4 & & \\
379 \hline 379 \hline
380 ARMv4T & ARM 7, ARM 9, Neo FreeRunner (OpenMoko) & \\ 380 ARMv4T & ARM 7, ARM 9, Neo FreeRunner (OpenMoko) & \\
385 \hline 385 \hline
386 ARMv7 & iPod touch, iPhone 3GS/4, Raspberry Pi 2 & VFP throughout available, armhf calling convention on some platforms \\ 386 ARMv7 & iPod touch, iPhone 3GS/4, Raspberry Pi 2 & VFP throughout available, armhf calling convention on some platforms \\
387 \hline 387 \hline
388 ARMv8 & iPhone 6 and higher & 64bit support \\ 388 ARMv8 & iPhone 6 and higher & 64bit support \\
389 \hline 389 \hline
390 \end{tabular} 390 \end{tabular*}
391 \caption{Overview of ARM Architecture, Platforms and Details} 391 \caption{Overview of ARM Architecture, Platforms and Details}
392 \end{table} 392 \end{table}
393 393
394 \newpage 394 \newpage
395 395