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comparison doc/manual/callconvs/callconv_arm32.tex @ 35:61edd9cf8026

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- armhf doc update
author cslag
date Tue, 15 Dec 2015 14:40:19 +0100
parents 645307d37731
children 00310bf92924
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34:645307d37731 35:61edd9cf8026
80 \item caller cleans up the stack 80 \item caller cleans up the stack
81 \item first four words are passed using r0-r3 81 \item first four words are passed using r0-r3
82 \item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters) 82 \item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters)
83 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack 83 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack
84 \item parameters \textless=\ 32 bits are passed as 32 bit words 84 \item parameters \textless=\ 32 bits are passed as 32 bit words
85 \item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack), although this doesn't seem to be specified in the ATPCS), with the loword coming first 85 \item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack, although this doesn't seem to be specified in the ATPCS), with the loword coming first
86 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3 86 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3
87 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc... (see {\bf return values}) 87 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc... (see {\bf return values})
88 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis) 88 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis)
89 \end{itemize} 89 \end{itemize}
90 90
150 \hline 150 \hline
151 Name & Brief description\\ 151 Name & Brief description\\
152 \hline 152 \hline
153 {\bf r0} & parameter 0, scratch, return value\\ 153 {\bf r0} & parameter 0, scratch, return value\\
154 {\bf r1} & parameter 1, scratch, return value\\ 154 {\bf r1} & parameter 1, scratch, return value\\
155 {\bf r2-r3} & parameters 2 and 3, scratch\\ 155 {\bf r2,r3} & parameters 2 and 3, scratch\\
156 {\bf r4-r6} & permanent\\ 156 {\bf r4-r6} & permanent\\
157 {\bf r7} & frame pointer, permanent\\ 157 {\bf r7} & frame pointer, permanent\\
158 {\bf r8-r11} & permanent\\ 158 {\bf r8-r11} & permanent\\
159 {\bf r12} & scratch\\ 159 {\bf r12} & scratch\\
160 {\bf r13} & stack pointer, permanent\\ 160 {\bf r13} & stack pointer, permanent\\
178 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3 178 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3
179 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc. (see {\bf return values}) 179 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc. (see {\bf return values})
180 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis) 180 \item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis)
181 \end{itemize} 181 \end{itemize}
182 182
183
184 \paragraph{Return values} 183 \paragraph{Return values}
185 \begin{itemize} 184 \begin{itemize}
186 \item return values \textless=\ 32 bits use r0 185 \item return values \textless=\ 32 bits use r0
187 \item 64 bit return values use r0 and r1 186 \item 64 bit return values use r0 and r1
188 \item if return value is a structure, the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0 187 \item if return value is a structure, the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0
231 standard (ATPCS) \cite{ATPCS} - however, the EABI requires the stack to be 230 standard (ATPCS) \cite{ATPCS} - however, the EABI requires the stack to be
232 8-byte aligned at function entries, as well as 64 bit parameters. The latter 231 8-byte aligned at function entries, as well as 64 bit parameters. The latter
233 are aligned on 8-byte boundaries on the stack and 2-registers for parameters 232 are aligned on 8-byte boundaries on the stack and 2-registers for parameters
234 passed via register. In order to achieve such an alignment, a register might 233 passed via register. In order to achieve such an alignment, a register might
235 have to be skipped for parameters passed via registers, or 4-bytes on the stack 234 have to be skipped for parameters passed via registers, or 4-bytes on the stack
236 for parameters passed via the stack. Refer to the Debian ARM EABI port wiki for more information \cite{armeabi}. 235 for parameters passed via the stack. Refer to the Debian ARM EABI port wiki
236 for more information \cite{armeabi}.
237 237
238 238
239 \paragraph{Status} 239 \paragraph{Status}
240 240
241 \begin{itemize} 241 \begin{itemize}
259 \hline 259 \hline
260 Name & Brief description\\ 260 Name & Brief description\\
261 \hline 261 \hline
262 {\bf R0} & parameter 0, scratch, return value\\ 262 {\bf R0} & parameter 0, scratch, return value\\
263 {\bf R1} & parameter 1, scratch, return value\\ 263 {\bf R1} & parameter 1, scratch, return value\\
264 {\bf R2-R3} & parameters 2 and 3, scratch\\ 264 {\bf R2,R3} & parameters 2 and 3, scratch\\
265 {\bf R4-R6} & permanent\\ 265 {\bf R4-R6} & permanent\\
266 {\bf R7} & frame pointer, permanent\\ 266 {\bf R7} & frame pointer, permanent\\
267 {\bf R8} & permanent\\ 267 {\bf R8} & permanent\\
268 {\bf R9} & permanent(iOS 2.0) and scratch (since iOS 3.0)\\ 268 {\bf R9} & permanent(iOS 2.0) and scratch (since iOS 3.0)\\
269 {\bf R10-R11}& permanent\\ 269 {\bf R10-R11}& permanent\\
270 {\bf R12} & scratch, intra-procedure scratch register (IP) used by dynamic linker\\ 270 {\bf R12} & scratch, intra-procedure scratch register (IP) used by dynamic linker\\
271 {\bf R13} & stack pointer, permanent\\ 271 {\bf R13} & stack pointer, permanent\\
272 {\bf R14} & link register, permanent\\ 272 {\bf R14} & link register, permanent\\
273 {\bf R15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\ 273 {\bf R15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
274 {\bf CPSR} & Program status register\\ 274 {\bf CPSR} & Program status register\\
275 {\bf D0-D7} & scratch. aliases S0-S15, on ARMv7 alsa as Q0-Q3. Not accessible from Thumb mode on ARMv6.\\ 275 {\bf D0-D7} & scratch. aliases S0-S15, on ARMv7 also as Q0-Q3. Not accessible from Thumb mode on ARMv6.\\
276 {\bf D8-D15} & permanent, aliases S16-S31, on ARMv7 alsa as Q4-A7. Not accesible from Thumb mode on ARMv6.\\ 276 {\bf D8-D15} & permanent, aliases S16-S31, on ARMv7 also as Q4-A7. Not accesible from Thumb mode on ARMv6.\\
277 {\bf D16-D31}& Only available in ARMv7, aliases Q8-Q15.\\ 277 {\bf D16-D31}& Only available in ARMv7, aliases Q8-Q15.\\
278 {\bf FPSCR} & VFP status register.\\ 278 {\bf FPSCR} & VFP status register.\\
279 \hline 279 \hline
280 \end{tabular} 280 \end{tabular}
281 \caption{Register usage on ARM Apple iOS} 281 \caption{Register usage on ARM Apple iOS}
290 290
291 291
292 \subsubsection{ARM hard float (armhf)} 292 \subsubsection{ARM hard float (armhf)}
293 293
294 294
295 Most debian-based Linux systems on ARMv7 platforms use a calling convention referred to as armhf, using 295 Most debian-based Linux systems on ARMv7 (or ARMv6 with FPU) platforms use a calling convention referred to
296 16 64-bit floating point registers of the FPU of the VFPv3-D16 extension to the ARM architecture. Code 296 as armhf, using 16 64-bit floating point registers of the FPU of the VFPv3-D16 extension to the ARM architecture.
297 is using the Thumb-2 instruction set. 297 The instruction set used for armhf is Thumb-2. Refer to the debian wiki for more information \cite{armhf}.
298
299 Code is little-endian, rest is similar to EABI, 8-byte aligned stack, etc..
298 300
299 \paragraph{Register usage} 301 \paragraph{Register usage}
300 302
301 \begin{table}[h] 303 \begin{table}[h]
302 \begin{tabular}{3 B} 304 \begin{tabular}{3 B}
303 \hline 305 \hline
304 Name & Brief description\\ 306 Name & Brief description\\
305 \hline 307 \hline
306 ... tbd 308 {\bf R0} & parameter 0, scratch, return value\\
309 {\bf R1} & parameter 1, scratch, return value\\
310 {\bf R2,R3} & parameters 2 and 3, scratch\\
311 {\bf R4,R5} & permanent\\
312 {\bf R6} & scratch\\
313 {\bf R7} & frame pointer, permanent\\
314 {\bf R8} & permanent\\
315 {\bf R9,R10} & scratch\\
316 {\bf R11} & permanent\\
317 {\bf R12} & scratch, intra-procedure scratch register (IP) used by dynamic linker\\
318 {\bf R13} & stack pointer, permanent\\
319 {\bf R14} & link register, permanent\\
320 {\bf R15} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
321 {\bf CPSR} & Program status register\\
322 {\bf S0-S15} & floating point arguments, single precision\\
323 {\bf D0-D7} & aliases S0-S15, floating point arguments, double precision\\
324 {\bf FPSCR} & VFP status register.\\
307 \hline 325 \hline
308 \end{tabular} 326 \end{tabular}
309 \caption{Register usage on armhf} 327 \caption{Register usage on armhf}
310 \end{table} 328 \end{table}
329
330 \paragraph{Parameter passing}
331
332 \begin{itemize}
333 \item stack parameter order: right-to-left
334 \item caller cleans up the stack
335 \item first four non-floating-point words are passed using r0-r3
336 \item first 16 single-precision, or 8 double-precision arguments are passed via s0-s15 or d0-d7, respectively
337 \item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters)
338 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack @@@?check doc
339 \item parameters \textless=\ 32 bits are passed as 32 bit words
340 \item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack, although this doesn't seem to be specified in the ATPCS), with the loword coming first @@@?check doc
341 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3 @@@?check doc
342 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc. (see {\bf return values})
343 \end{itemize}
344
345 \paragraph{Return values}
346 \begin{itemize}
347 \item return values \textless=\ 32 bits use r0
348 \item 64 bit return values use r0 and r1
349 \item if return value is a structure, the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0
350 \end{itemize}
351
352
311 353
312 354
313 \subsubsection{Architectures} 355 \subsubsection{Architectures}
314 356
315 The ARM architecture family contains several revisions with capabilities and 357 The ARM architecture family contains several revisions with capabilities and