comparison doc/manual/callconvs/callconv_sparc.tex @ 194:41d6945f5858

- sparc doc improvements (esp. for sparc64)
author Tassilo Philipp
date Sat, 18 Mar 2017 19:08:45 +0100
parents 600bd90afdb7
children 53c42b1d9f8b
comparison
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193:600bd90afdb7 194:41d6945f5858
32 \subsubsection{SPARC (32-bit) Calling Convention} 32 \subsubsection{SPARC (32-bit) Calling Convention}
33 33
34 \paragraph{Register usage} 34 \paragraph{Register usage}
35 35
36 \begin{itemize} 36 \begin{itemize}
37 \item 32 32-bit integer/pointer registers 37 \item 32 single floating point registers (f0-f31, usable as 8 quad precision q0,q4,q8,...,q28, 16 double precision d0,d2,d4,...,d30)
38 \item 32 floating point registers (usable as 8 quad precision, 16 double precision or 32 single precision registers) 38 \item 32 32-bit integer/pointer registers out of a bigger (vendor/model dependent) number that are accessible at a time (8 are global ones (g*), whereas the remaining 24 form a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones)
39 \item 32 registers are accessible at a time (8 are global ones (g*), whereas the rest forms a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones)
40 \item calling a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore) 39 \item calling a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore)
41 \end{itemize} 40 \end{itemize}
42 41
43 \begin{table}[h] 42 \begin{table}[h]
44 \begin{tabular*}{0.95\textwidth}{lll} 43 \begin{tabular*}{0.95\textwidth}{lll}
45 Name & Alias & Brief description\\ 44 Name & Alias & Brief description\\
46 \hline 45 \hline
47 {\bf \%g0} & & Read-only, hardwired to 0 \\ 46 {\bf \%g0} & \%r0 & Read-only, hardwired to 0 \\
48 {\bf \%g1-\%g7} & & Global \\ 47 {\bf \%g1-\%g7} & \%r1-\%r7 & Global \\
49 {\bf \%o0 and \%i0} & & Output and input argument 0, return value \\ 48 {\bf \%o0,\%o1 and \%i0,\%i1} & \%r8,\%r9 and \%r24,\%r25 & Output and input argument registers, return value \\
50 {\bf \%o1-\%o5 and \%i1-\%i5} & & Output and input argument registers \\ 49 {\bf \%o2-\%o5 and \%i2-\%i5} & \%r10-\%r13 and \%r26-\%r29 & Output and input argument registers \\
51 {\bf \%o6 and \%i6} & & Stack and frame pointer \\ 50 {\bf \%o6 and \%i6} & \%r14 and \%r30, \%sp and \%fp & Stack and frame pointer \\
52 {\bf \%o7 and \%i7} & & Return address (caller writes to o7, callee uses i7) \\ 51 {\bf \%o7 and \%i7} & \%r15 and \%r31 & Return address (caller writes to o7, callee uses i7) \\
52 {\bf \%l0-\%l7} & \%r16-\%r23 & preserve \\
53 {\bf \%f0,\%f1} & & Floating point return value \\
54 {\bf \%f2-\%f31} & & scratch \\
53 \end{tabular*} 55 \end{tabular*}
54 \caption{Register usage on sparc calling convention} 56 \caption{Register usage on sparc calling convention}
55 \end{table} 57 \end{table}
56 58
57 \paragraph{Parameter passing} 59 \paragraph{Parameter passing}
100 \hhline{~-~~} 102 \hhline{~-~~}
101 \end{tabular} 103 \end{tabular}
102 \\ 104 \\
103 \\ 105 \\
104 \\ 106 \\
105 \caption{Stack layout on sparc calling convention} 107 \caption{Stack layout on sparc32 calling convention}
106 \end{figure} 108 \end{figure}
107 109