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- review and fixes, cleanup, amendments to calling convention appendix of manual
author Tassilo Philipp
date Fri, 22 Nov 2019 23:11:56 +0100
parents a1fcb3e02270
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1 %////////////////////////////////////////////////////////////////////////////// 1 %//////////////////////////////////////////////////////////////////////////////
2 % 2 %
3 % Copyright (c) 2007,2009 Daniel Adler <dadler@uni-goettingen.de>, 3 % Copyright (c) 2007-2019 Daniel Adler <dadler@uni-goettingen.de>,
4 % Tassilo Philipp <tphilipp@potion-studios.com> 4 % Tassilo Philipp <tphilipp@potion-studios.com>
5 % 5 %
6 % Permission to use, copy, modify, and distribute this software for any 6 % Permission to use, copy, modify, and distribute this software for any
7 % purpose with or without fee is hereby granted, provided that the above 7 % purpose with or without fee is hereby granted, provided that the above
8 % copyright notice and this permission notice appear in all copies. 8 % copyright notice and this permission notice appear in all copies.
15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 % 17 %
18 %////////////////////////////////////////////////////////////////////////////// 18 %//////////////////////////////////////////////////////////////////////////////
19 19
20 \subsection{MIPS32 Calling Convention} 20 \subsection{MIPS32 Calling Conventions}
21 21
22 \paragraph{Overview} 22 \paragraph{Overview}
23 23
24 Multiple revisions of the MIPS Instruction set exist, namely MIPS I, MIPS II, MIPS III, MIPS IV, MIPS32 and MIPS64. 24 Multiple revisions of the MIPS Instruction set exist, namely MIPS I, MIPS II, MIPS III, MIPS IV, MIPS32 and MIPS64.
25 Nowadays, MIPS32 and MIPS64 are the main ones used for 32-bit and 64-bit instruction sets, respectively.\\ 25 Nowadays, MIPS32 and MIPS64 are the main ones used for 32-bit and 64-bit instruction sets, respectively.\\
39 39
40 Currently, dyncall supports for MIPS 32-bit architectures the widely-used O32 calling convention (for all four combinations of big/little-endian, and soft/hard-float targets), 40 Currently, dyncall supports for MIPS 32-bit architectures the widely-used O32 calling convention (for all four combinations of big/little-endian, and soft/hard-float targets),
41 as well as EABI (little-endian/hard-float, which is used on the Homebrew SDK for the Playstation Portable). \product{dyncall} currently does not support MIPS16e 41 as well as EABI (little-endian/hard-float, which is used on the Homebrew SDK for the Playstation Portable). \product{dyncall} currently does not support MIPS16e
42 (contrary to the like-minded ARM-THUMB, which is supported). Both, calls and callbacks are supported. 42 (contrary to the like-minded ARM-THUMB, which is supported). Both, calls and callbacks are supported.
43 43
44
45 \newpage
46
47
44 \subsubsection{MIPS EABI 32-bit Calling Convention} 48 \subsubsection{MIPS EABI 32-bit Calling Convention}
49
50 % This is about hardware floating point targtes, there are also softfloat ones @@@
45 51
46 \paragraph{Register usage} 52 \paragraph{Register usage}
47 53
48 \begin{table}[h] 54 \begin{table}[h]
49 \begin{tabular*}{0.95\textwidth}{lll} 55 \begin{tabular*}{0.95\textwidth}{lll}
50 Name & Alias & Brief description\\ 56 Name & Alias & Brief description\\
51 \hline 57 \hline
52 {\bf \$0} & {\bf \$zero} & hardware zero \\ 58 {\bf \$0} & {\bf \$zero} & hardware zero, scratch \\
53 {\bf \$1} & {\bf \$at} & assembler temporary \\ 59 {\bf \$1} & {\bf \$at} & assembler temporary, scratch \\
54 {\bf \$2-\$3} & {\bf \$v0-\$v1} & integer results \\ 60 {\bf \$2-\$3} & {\bf \$v0-\$v1} & integer results, scratch \\
55 {\bf \$4-\$11} & {\bf \$a0-\$a7} & integer arguments, or double precision float arguments\\ 61 {\bf \$4-\$11} & {\bf \$a0-\$a7} & integer arguments, or double precision float arguments, scratch \\
56 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & integer temporaries \\ 62 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & integer temporaries, scratch \\
57 {\bf \$25} & {\bf \$t9} & integer temporary, holds address of called function for PIC calls (by convention) \\ 63 {\bf \$25} & {\bf \$t9} & integer temporary, address of callee for PIC calls (by convention), scratch \\
58 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserved \\ 64 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserve \\
59 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & reserved for kernel \\ 65 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & reserved for kernel \\
60 {\bf \$28} & {\bf \$gp} & global pointer, preserve \\ 66 {\bf \$28} & {\bf \$gp} & global pointer, preserve \\
61 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\ 67 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\
62 {\bf \$30} & {\bf \$s8} & frame pointer, preserve \\ 68 {\bf \$30} & {\bf \$s8/\$fp} & frame pointer (some assemblers name it \$fp), preserve \\
63 {\bf \$31} & {\bf \$ra} & return address, preserve \\ 69 {\bf \$31} & {\bf \$ra} & return address, preserve \\
64 {\bf hi, lo} & & multiply/divide special registers \\ 70 {\bf hi, lo} & & multiply/divide special registers \\
65 {\bf \$f0,\$f2} & & float results \\ 71 {\bf \$f0,\$f2} & & float results, scratch \\
66 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & float temporaries \\ 72 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & float temporaries, scratch \\
67 {\bf \$f12-\$f19} & & single precision float arguments \\ 73 {\bf \$f12-\$f19} & & single precision float arguments, scratch \\
68 \end{tabular*} 74 \end{tabular*}
69 \caption{Register usage on MIPS32 EABI calling convention} 75 \caption{Register usage on MIPS32 EABI calling convention}
70 \end{table} 76 \end{table}
71 77
72 \paragraph{Parameter passing} 78 \paragraph{Parameter passing}
75 \item Stack grows down 81 \item Stack grows down
76 \item Stack parameter order: right-to-left 82 \item Stack parameter order: right-to-left
77 \item Caller cleans up the stack 83 \item Caller cleans up the stack
78 \item first 8 integers (\textless=\ 32bit) are passed in registers \$a0-\$a7 84 \item first 8 integers (\textless=\ 32bit) are passed in registers \$a0-\$a7
79 \item first 8 single precision floating point arguments are passed in registers \$f12-\$f19 85 \item first 8 single precision floating point arguments are passed in registers \$f12-\$f19
86 \item 64-bit stack arguments are always aligned to 8 bytes
87 \item 64-bit integers or double precision floats are passed in two general purpose registers starting at an even register number, skipping one odd register
80 \item if either integer or float registers are used up, the stack is used 88 \item if either integer or float registers are used up, the stack is used
81 \item 64-bit stack arguments are always aligned to 8 bytes 89 \item if the callee takes the address of one of the parameters and uses it to address other unnamed parameters (e.g. varargs) it has to copy - in its prolog - the the argument registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed integer parameters require saving, though) % @@@ seems to *ONLY* spill with varargs, never for any other reason
82 \item 64-bit integers or double precision floats are passed on two general purpose registers starting at an even register number, skipping one odd register 90 \item float registers don't seem to ever need to be saved that way, because floats passed to an ellipsis function are promoted to doubles, which in turn are passed in a? register pairs, so only \$a0-\$a7 are need to be spilled
83 \item \$a0-\$a7 and \$f12-\$f19 are not required to be preserved
84 \item results are returned in \$v0 (32-bit), \$v0 and \$v1 (64-bit), \$f0 or \$f0 and \$f2 (2 $\times$ 32 bit float e.g. complex) 91 \item results are returned in \$v0 (32-bit), \$v0 and \$v1 (64-bit), \$f0 or \$f0 and \$f2 (2 $\times$ 32 bit float e.g. complex)
85 \end{itemize} 92 \end{itemize}
86 93
87 \paragraph{Stack layout} 94 \paragraph{Stack layout}
88 95
96 % verified/amended: TP nov 2019 (see also doc/disas_examples/mips.eabi.disas)
89 Stack directly after function prolog:\\ 97 Stack directly after function prolog:\\
90 98
91 \begin{figure}[h] 99 \begin{figure}[h]
92 \begin{tabular}{5|3|1 1} 100 \begin{tabular}{5|3|1 1}
93 \hhline{~-~~} 101 & \vdots & & \\
94 & \vdots & & \\ 102 \hhline{~=~~}
95 \hhline{~=~~} 103 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\
96 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ 104 \hhline{~-~~}
97 \hhline{~-~~} 105 local data & & & \\
98 local data & & & \\ 106 \hhline{~-~~}
99 \hhline{~-~~} 107 \mrlbrace{6}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\
100 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ 108 & \ldots & & \\
101 & \ldots & & \\ 109 & first arg passed via stack & & \\
102 & \ldots & & \\
103 \hhline{~=~~} 110 \hhline{~=~~}
104 register save area (with return address) & & & \mrrbrace{5}{current frame} \\ 111 & \$a7 & \mrrbrace{3}{spill area (if needed)} & \mrrbrace{6}{current frame} \\
105 \hhline{~-~~} 112 & \ldots & & \\
106 local data & & & \\ 113 & \$a? (first unnamed reg) & & \\
107 \hhline{~-~~} 114 \hhline{~-~~}
108 parameter area & & & \\ 115 register save area (with return address) & & & \\
109 \hhline{~-~~} 116 \hhline{~-~~}
110 & \vdots & & \\ 117 local data & & & \\
111 \hhline{~-~~} 118 \hhline{~-~~}
119 parameter area & \vdots & & \\
112 \end{tabular} 120 \end{tabular}
113 \caption{Stack layout on mips32 eabi calling convention} 121 \caption{Stack layout on MIPS EABI 32-bit calling convention}
114 \end{figure} 122 \end{figure}
115 123
124
116 \newpage 125 \newpage
126
117 127
118 \subsubsection{MIPS O32 32-bit Calling Convention} 128 \subsubsection{MIPS O32 32-bit Calling Convention}
119 129
120 \paragraph{Register usage} 130 \paragraph{Register usage}
121 131
131 {\bf \$25} & {\bf \$t9} & temporary, holds address of called function for PIC calls (by convention) \\ 141 {\bf \$25} & {\bf \$t9} & temporary, holds address of called function for PIC calls (by convention) \\
132 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserved \\ 142 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserved \\
133 {\bf \$26,\$27} & {\bf \$k0,\$k1} & reserved for kernel \\ 143 {\bf \$26,\$27} & {\bf \$k0,\$k1} & reserved for kernel \\
134 {\bf \$28} & {\bf \$gp} & global pointer, preserved by caller \\ 144 {\bf \$28} & {\bf \$gp} & global pointer, preserved by caller \\
135 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\ 145 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\
136 {\bf \$30} & {\bf \$fp} & frame pointer, preserve \\ 146 {\bf \$30} & {\bf \$s8/\$fp} & frame pointer (some assemblers name it \$fp), preserve \\
137 {\bf \$31} & {\bf \$ra} & return address, preserve \\ 147 {\bf \$31} & {\bf \$ra} & return address, preserve \\
138 {\bf hi, lo} & & multiply/divide special registers \\ 148 {\bf hi, lo} & & multiply/divide special registers \\
139 {\bf \$f0-\$f3} & & only on hard-float targets: float return value, scratch \\ 149 {\bf \$f0-\$f3} & & only on hard-float targets: float return value, scratch \\
140 {\bf \$f4-\$f11,\$f16-\$f19} & & only on hard-float targets: float temporaries, scratch \\ 150 {\bf \$f4-\$f11,\$f16-\$f19} & & only on hard-float targets: float temporaries, scratch \\
141 {\bf \$f12-\$f15} & & only on hard-float targets: first floating point arguments, scratch \\ 151 {\bf \$f12-\$f15} & & only on hard-float targets: first floating point arguments, scratch \\
163 \item single precision float parameters (32 bit) are right-justified in their 8-byte slot on the stack on big endian targets, as they aren't promoted @@@ 173 \item single precision float parameters (32 bit) are right-justified in their 8-byte slot on the stack on big endian targets, as they aren't promoted @@@
164 \end{itemize} 174 \end{itemize}
165 175
166 \paragraph{Stack layout} 176 \paragraph{Stack layout}
167 177
178 % verified/amended: TP nov 2019 (see also doc/disas_examples/mips.o32.disas)
168 Stack directly after function prolog:\\ 179 Stack directly after function prolog:\\
169 180
170 \begin{figure}[h] 181 \begin{figure}[h]
171 \begin{tabular}{5|3|1 1} 182 \begin{tabular}{5|3|1 1}
172 \hhline{~-~~} 183 & \vdots & & \\
173 & \vdots & & \\ 184 \hhline{~=~~}
174 \hhline{~=~~} 185 register save area (with return address) & \hspace{4cm} & & \mrrbrace{10}{caller's frame} \\
175 register save area (and padding) & \hspace{4cm} & & \\ 186 \hhline{~-~~}
176 \hhline{~-~~} 187 local data (and padding) & & & \\
177 local data (and padding) & & & \mrrbrace{10}{caller's frame} \\ 188 \hhline{~-~~}
178 \hhline{~-~~} 189 \mrlbrace{8}{parameter area} & padding (if needed) & & \\
179 \mrlbrace{8}{parameter area} & padding (if needed) & & \\ 190 & last arg & \mrrbrace{3}{stack parameters} & \\
180 & \ldots & \mrrbrace{3}{stack parameters} & \\ 191 & \ldots & & \\
181 & \ldots & & \\ 192 & first arg passed via stack & & \\
182 & \ldots & & \\ 193 & \$a3 & \mrrbrace{4}{spill area} & \\
183 & \$a3 & \mrrbrace{4}{spill area} & \\ 194 & \$a2 & & \\
184 & \$a2 & & \\ 195 & \$a1 & & \\
185 & \$a1 & & \\ 196 & \$a0 & & \\
186 & \$a0 & & \\ 197 \hhline{~=~~}
187 \hhline{~-~~} 198 register save area & & & \mrrbrace{3}{current frame} \\
188 register save area (with return address) & & & \\ 199 \hhline{~-~~}
189 \hhline{~=~~} 200 local data & & & \\
190 local data & & & \mrrbrace{5}{current frame} \\ 201 \hhline{~-~~}
191 \hhline{~-~~} 202 parameter area & \vdots & & \\
192 parameter area & & & \\
193 & \vdots & & \\
194 \hhline{~-~~}
195 \end{tabular} 203 \end{tabular}
196 \caption{Stack layout on MIPS O32 calling convention} 204 \caption{Stack layout on MIPS O32 calling convention}
197 \end{figure} 205 \end{figure}
198 206
199 \newpage 207 \newpage