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annotate doc/manual/callconvs/callconv_ppc64.tex @ 499:fc614cb865c6
- doc and disasexample additions specific to non-trivial C++ aggregates as return values (incl. fixes to doc and additional LSB specific PPC32 section)
| author | Tassilo Philipp |
|---|---|
| date | Mon, 04 Apr 2022 15:50:52 +0200 |
| parents | ead041d93e36 |
| children | 0909837648d2 |
| rev | line source |
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| 0 | 1 %////////////////////////////////////////////////////////////////////////////// |
| 2 % | |
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3 % Copyright (c) 2007-2022 Daniel Adler <dadler@uni-goettingen.de>, |
| 0 | 4 % Tassilo Philipp <tphilipp@potion-studios.com> |
| 5 % | |
| 6 % Permission to use, copy, modify, and distribute this software for any | |
| 7 % purpose with or without fee is hereby granted, provided that the above | |
| 8 % copyright notice and this permission notice appear in all copies. | |
| 9 % | |
| 10 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| 11 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| 12 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| 13 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| 14 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| 15 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| 16 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| 17 % | |
| 18 %////////////////////////////////////////////////////////////////////////////// | |
| 19 | |
| 20 % ================================================== | |
| 21 % PowerPC 64 | |
| 22 % ================================================== | |
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23 \subsection{PowerPC (64bit) Calling Conventions} |
| 0 | 24 |
| 25 \paragraph{Overview} | |
| 26 | |
| 27 \begin{itemize} | |
| 331 | 28 \item Word size is 32 bits for historical reasons |
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29 \item Doublework size is 64 bits. |
| 0 | 30 \item Big endian (MSB) and litte endian (LSB) operating modes. |
| 31 \item Apple Mac OS X/Darwin PPC is specified in "Mac OS X ABI Function Call Guide"\cite{ppcMacOSX}. It uses Big Endian (MSB). | |
| 32 \item Linux PPC 64-bit ABI is specified in "64-bit PowerPC ELF Application Binary Interface Supplement"\cite{ppcelf64abi} which is based on "System V ABI". | |
| 33 \end{itemize} | |
| 34 | |
| 35 \paragraph{\product{dyncall} support} | |
| 36 | |
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37 \product{Dyncall} and \product{dyncallback} are supported for PowerPC (64bit) |
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38 Big Endian and Little Endian ELF ABIs on System V systems. Mac OS X is not |
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39 supported.\\ |
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40 \product{Dyncall} can also be used to issue syscalls by using the syscall |
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41 number as target parameter and selecting the correct mode. |
| 0 | 42 |
| 43 | |
| 44 \subsubsection{PPC64 ELF ABI} | |
| 45 | |
| 46 \paragraph{Registers and register usage} | |
| 47 | |
| 331 | 48 \begin{table}[h] |
| 49 \begin{tabular*}{0.95\textwidth}{3 B} | |
| 50 Name & Brief description\\ | |
| 51 \hline | |
| 52 {\bf gpr0} & scratch\\ | |
| 53 {\bf gpr1} & stack pointer\\ | |
| 54 {\bf gpr2} & TOC base ptr (offset table and data for position independent code), scratch\\ | |
| 55 {\bf gpr3} & return value, parameter 0 for integer or pointer, scratch\\ | |
| 56 {\bf gpr4-gpr10} & parameter 1-7 for integer or pointer parameters, scratch\\ | |
| 0 | 57 |
| 331 | 58 {\bf gpr11} & env pointer if needed, scratch\\ |
| 59 {\bf gpr12} & used for exception handling and glink code, scratch\\ | |
| 60 {\bf gpr13} & used for system thread ID, preserve\\ | |
| 61 {\bf gpr14-31} & preserve\\ | |
| 62 {\bf fpr0} & scratch\\ | |
| 63 {\bf fpr1-fpr4} & floating point return value, floating point parameter 0-3 (always double precision)\\ | |
| 64 {\bf fpr5-fpr13} & floating point parameters 4-12 (always double precision)\\ | |
| 65 {\bf fpr14-fpr31} & preserve\\ | |
| 66 {\bf v0-v1} & scratch\\ | |
| 67 {\bf v2-v13} & vector parameters\\ | |
| 68 {\bf v14-v19} & scratch\\ | |
| 69 {\bf v20-v31} & preserve\\ | |
| 70 {\bf lr} & link-register, scratch\\ | |
| 71 {\bf ctr} & count-register, scratch\\ | |
| 72 {\bf xer} & fixed point exception register, scratch\\ | |
| 73 {\bf fpscr} & floating point status and control register, scratch\\ | |
| 74 {\bf cr0-cr7} & conditional register fields, each 4-bit wide (cr0-cr1 and cr5-cr7 are scratch)\\ | |
| 75 \end{tabular*} | |
| 76 \caption{Register usage on PowerPC 64-Bit ELF ABI} | |
| 77 \end{table} | |
| 0 | 78 |
| 79 \paragraph{Parameter passing} | |
| 80 | |
| 123 | 81 \begin{itemize} |
| 331 | 82 \item stack grows down |
| 83 \item stack parameter order: right-to-left | |
| 84 \item caller cleans up the stack | |
| 85 \item stack is always 16 byte aligned | |
| 86 \item the stack pointer must be atomically updated (to avoid any timing window in which an interrupt can occur with a partially updated stack), usually with the stdu (store doubleword with update) instruction | |
| 87 \item the first 8 integer parameters are passed in registers gpr3-gpr10 | |
| 88 \item the first 13 floating point parameters are passed in registers fpr1-fpr13 | |
| 89 \item preserved registers are saved using a defined order (from high to low addresses): | |
| 90 fpr* (64bit aligned), | |
| 91 gpr*, | |
| 92 VRSAVE save word (32 bits), | |
| 93 padding for alignment (4 or 12 bytes), | |
| 94 v* (128bit aligned) | |
| 95 \item if a floating point parameter is passed via a register, a gpr registers is skipped for subsequent integer parameters | |
| 96 \item the caller pushes subsequent parameters onto the stack | |
| 97 \item single precision floating point values use the second word in a doubleword | |
| 98 \item a quad precision floating point argument is passed as two consecutive double precision ones | |
| 99 \item integer types \textless\ 64 bit are sign or zero extended and use a doubleword | |
| 100 \item ellipsis calls take floating point values in int and float registers (single precision floats are promoted to double precision as | |
| 101 required by ellipsis calls) | |
| 102 \item space for all potential gpr* register passed arguments is reserved in the stack parameter area (in order to spill the parameters if | |
| 103 needed - e.g. varargs), meaning a minimum of 64 bytes to hold gpr3-gpr10 | |
| 104 \item all nonvector parameters are aligned on 8-byte boundaries | |
| 105 \item vector parameters are aligned on 16-byte boundaries | |
| 125 | 106 \item integer parameters \textless\ 64 bit are right-justified (meaning occupy higher-address bytes) in their 8-byte slot on the stack, requiring extra-care for big-endian targets |
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107 \item aggregates (struct, union) are passed as a sequence of doublewords (following above rules for doublewords) |
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108 \item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate |
| 123 | 109 \end{itemize} |
| 0 | 110 |
| 111 | |
| 112 \paragraph{Return values} | |
| 113 | |
| 331 | 114 \begin{itemize} |
| 115 \item return values of integer \textless=\ 32bit or pointer type use gpr3 and are zero or sign extended depending on their type | |
| 116 \item 64 bit integers use gpr3 | |
| 117 \item floating point values are returned via fpr1 | |
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118 \item for any aggregate (struct, union), the caller allocates space, passes pointer to it to the callee as a hidden first param |
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119 (meaning in gpr3), and callee writes return value to this space; the ptr to the aggregate is returned in gpr3 |
| 331 | 120 \end{itemize} |
| 0 | 121 |
| 122 | |
| 123 \paragraph{Stack layout} | |
| 124 | |
| 331 | 125 Stack frame is always 16-byte aligned. |
| 126 % verified/amended: TP nov 2019 (see also doc/disas_examples/ppc64.elfabi.disas) | |
| 127 Stack directly after function prolog:\\ | |
| 0 | 128 |
| 331 | 129 \begin{figure}[h] |
| 130 \begin{tabular}{5|3|1 1} | |
| 131 & \vdots & & \\ | |
| 132 \hhline{~=~~} | |
| 133 register save area & \hspace{4cm} & & \mrrbrace{14}{caller's frame} \\ | |
| 134 \hhline{~-~~} | |
| 135 local data & & & \\ | |
| 136 \hhline{~-~~} | |
| 137 \mrlbrace{6}{parameter area} & last arg & \mrrbrace{3}{stack parameters} & \\ | |
| 138 & \ldots & & \\ | |
| 139 & arg 8 & & \\ | |
| 140 & gpr10 & \mrrbrace{3}{spill area (as needed)} & \\ | |
| 141 & \ldots & & \\ | |
| 142 & gpr3 & & \\ | |
| 143 \hhline{~-~~} | |
| 144 \mrlbrace{6}{linkage area} & TOC ptr reg & & \\ | |
| 145 & reserved & & \\ | |
| 146 & reserved & & \\ | |
| 147 & return address (callee saved) & & \\ | |
| 148 & condition reg (callee saved) & & \\ | |
| 149 & parent stack frame pointer & & \\ | |
| 150 \hhline{~=~~} | |
| 151 register save area & & & \mrrbrace{4}{current frame} \\ | |
| 152 \hhline{~-~~} | |
| 153 local data & & & \\ | |
| 154 \hhline{~-~~} | |
| 155 parameter area & & & \\ | |
| 156 \hhline{~-~~} | |
| 157 linkage area & \vdots & & \\ | |
| 158 \end{tabular} | |
| 159 \caption{Stack layout on ppc64 ELF ABI} | |
| 160 \end{figure} | |
| 161 | |
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162 |
| 467 | 163 \clearpage |
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164 |
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165 \subsubsection{System V syscalls} |
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166 |
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167 \paragraph{Parameter passing} |
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168 |
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169 \begin{itemize} |
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170 \item syscall is issued via the {\em sc} instruction |
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171 \item kernel destroys registers r13 |
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172 \item syscall number is set in r0 |
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173 \item params are passed in registers r3 through r10 |
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174 \item no stack in use, meaning syscalls are in theory limited to eight arguments |
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175 \item register r3 holds the return value, overflow flag in conditional register cr0 signals errors in syscall |
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176 \end{itemize} |
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177 |