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1 %
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2 % Copyright (c) 2014,2015 Daniel Adler <dadler@uni-goettingen.de>,
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3 % Tassilo Philipp <tphilipp@potion-studios.com>
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4 %
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5 % Permission to use, copy, modify, and distribute this software for any
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6 % purpose with or without fee is hereby granted, provided that the above
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7 % copyright notice and this permission notice appear in all copies.
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8 %
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9 % THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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10 % WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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11 % MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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12 % ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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13 % WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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14 % ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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15 % OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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16 %
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17
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18 % ==================================================
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19 % ARM64
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20 % ==================================================
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21 \subsection{ARM64 Calling Convention}
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22
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23 \paragraph{Overview}
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24
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25 ARMv8 introduced the AArch64 calling convention. ARM64 chips can be run in 64 or 32bit mode, but not by the same process. Interworking is only intre-process.\\
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26 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due to historical reasons (terminology
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27 didn't change from ARM32).\\
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28 For more details, take a look at the Procedure Call Standard for the ARM 64-bit Architecture \cite{AAPCS64}.
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29
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30
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31 \paragraph{\product{dyncall} support}
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32
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33 The \product{dyncall} library supports the ARM 64-bit AArch64 PCS ABI, for calls and callbacks.
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34
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35 \subsubsection{AAPCS64 Calling Convention}
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36
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37 \paragraph{Registers and register usage}
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38
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39 ARM64 features thirty-one 64 bit general purpose registers, namely x0-x30.
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40 Also, there is SP, a register with restricted use, used for the stack pointer,
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41 and PC dedicated as program counter. Additionally, there are thirty-two 128 bit
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42 registers v0-v31, to be used as SIMD and floating point registers, referred to
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43 as q0-q31, d0-d31 and s0-s31, respectively, depending on their use:\\
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44
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45 \begin{table}[h]
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46 \begin{tabular*}{0.95\textwidth}{3 B}
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47 Name & Brief description\\
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48 \hline
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49 {\bf x0-x7} & parameters, scratch, return value\\
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50 {\bf x8} & indirect result location pointer\\
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51 {\bf x9-x15} & scratch\\
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52 {\bf x16} & permanent in some cases, can have special function (IP0), see doc\\
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53 {\bf x17} & permanent in some cases, can have special function (IP1), see doc\\
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54 {\bf x18} & reserved as platform register, advised not to be used for handwritten, portable asm, see doc \\
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55 {\bf x19-x28} & permanent\\
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56 {\bf x29} & permanent, frame pointer\\
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57 {\bf x30} & permanent, link register\\
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58 {\bf SP} & permanent, stack pointer\\
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59 {\bf PC} & program counter\\
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76
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60 \end{tabular*}
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61 \caption{Register usage on arm64}
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62 \end{table}
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63
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64 \paragraph{Parameter passing}
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65
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66 \begin{itemize}
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67 \item stack parameter order: right-to-left
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68 \item caller cleans up the stack
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69 \item first 8 integer arguments are passed using x0-x7
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70 \item first 8 floating point arguments are passed using d0-d7
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71 \item subsequent parameters are pushed onto the stack
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72 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first 8 integer and 8 floating-point registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed parameters require saving, though)
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73 \item structures and unions are passed by value, with the first four words of the parameters in r0-r3
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74 \item if return value is a structure, a pointer pointing to the return value's space is passed in r0, the first parameter in r1, etc... (see {\bf return values})
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75 \item stack is required to be throughout eight-byte aligned
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76 \end{itemize}
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77
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78 \paragraph{Return values}
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79 \begin{itemize}
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80 \item integer return values use x0
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81 \item floating-point return values use d0
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82 \item otherwise, the caller allocates space, passes pointer to it to the callee through x8, and callee writes return value to this space
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83 \end{itemize}
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84
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85 \paragraph{Stack layout}
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86
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87 Stack directly after function prolog:\\
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88
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89 \begin{figure}[h]
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90 \begin{tabular}{5|3|1 1}
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91 \hhline{~-~~}
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92
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92 & \vdots & & \\
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93 \hhline{~=~~}
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94 register save area & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\
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95 \hhline{~-~~}
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96 local data & & & \\
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97 \hhline{~-~~}
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98 \mrlbrace{13}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\
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99 & \ldots & & \\
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100 & \ldots & & \\
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101 \hhline{~=~~}
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102 & x0 & \mrrbrace{10}{spill area (if needed)} & \mrrbrace{15}{current frame} \\
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103 & x1 & & \\
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104 & \ldots & & \\
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105 & x2 & & \\
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106 & x7 & & \\
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107 & d0 & & \\
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108 & d1 & & \\
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109 & \ldots & & \\
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110 & d2 & & \\
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111 & d7 & & \\
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112 \hhline{~-~~}
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113 register save area & & & \\
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114 \hhline{~-~~}
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115 local data & & & \\
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116 \hhline{~-~~}
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117 link and frame register & x30 & & \\
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118 & x29 & & \\
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119 \hhline{~-~~}
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120 parameter area & \vdots & & \\
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121 \hhline{~-~~}
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122 \end{tabular}
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123 \caption{Stack layout on arm64}
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124 \end{figure}
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125
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126 \newpage
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127
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128
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129 \subsubsection{Apple's ARM64 Function Calling Conventions}
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130
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131 \paragraph{Overview}
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132
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133 Apple's ARM64 calling convention is based on the AAPCS64 standard, however, diverges in some ways.
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134 Only the differences are listed here, for more details, take a look at Apple's official documentation \cite{AppleARM64}.
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135
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136 \begin{itemize}
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137 \item arguments passed via stack use only the space they need, but are subject to the type alignment requirements (which is 1 byte for char and bool, 2 for short, 4 for int and 8 for every other type)
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138 \item caller is required to sign and zero-extend arguments smaller than 32bits
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139 \end{itemize}
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140
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