changeset 650:4e40299cc673

- doc tweak
author Tassilo Philipp
date Thu, 07 Mar 2024 10:23:16 +0100
parents 0909837648d2
children cab0031c6691
files doc/manual/callconvs/callconv_riscv64.tex
diffstat 1 files changed, 3 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/doc/manual/callconvs/callconv_riscv64.tex	Thu Feb 22 17:49:07 2024 +0100
+++ b/doc/manual/callconvs/callconv_riscv64.tex	Thu Mar 07 10:23:16 2024 +0100
@@ -83,7 +83,7 @@
 \item first 8 floating point arguments are passed using f10-f17/fa0-fa7
 \item 128 bit arguments passed via registers are passed in even-odd register pairs (skipping a register, if necessary, which remains unused)
 \item aggregates (struct, union) \textless=\ 16 bytes in size are passed via registers (but only in float registers if members are either one or two floating point non-union and non-array members)
-\item arguments \textgreater 128 bits are passed as a pointer pointing to the argument (pointer to a copy, if needed)
+\item arguments \textgreater 128 bits are passed as a pointer to the argument (to a copy, if needed)
 \item subsequent parameters are pushed onto the stack
 \item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first 8 integer
 and 8 floating-point registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed integer parameters require saving, though)
@@ -103,6 +103,8 @@
 a0 as hidden param, and callee writes return value to this space
 \end{itemize}
 
+\clearpage
+
 \paragraph{Stack layout}
 
 % verified: TP feb 2024 (see also doc/disas_examples/riscv64.rvg.disas)