# HG changeset patch # User Tassilo Philipp # Date 1489860525 -3600 # Node ID 41d6945f58583bf01142cb7edb23638d95489678 # Parent 600bd90afdb7f7e61372d81d17b5164b910772a9 - sparc doc improvements (esp. for sparc64) diff -r 600bd90afdb7 -r 41d6945f5858 doc/manual/callconvs/callconv_sparc.tex --- a/doc/manual/callconvs/callconv_sparc.tex Tue Mar 14 03:25:12 2017 +0100 +++ b/doc/manual/callconvs/callconv_sparc.tex Sat Mar 18 19:08:45 2017 +0100 @@ -34,22 +34,24 @@ \paragraph{Register usage} \begin{itemize} -\item 32 32-bit integer/pointer registers -\item 32 floating point registers (usable as 8 quad precision, 16 double precision or 32 single precision registers) -\item 32 registers are accessible at a time (8 are global ones (g*), whereas the rest forms a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones) +\item 32 single floating point registers (f0-f31, usable as 8 quad precision q0,q4,q8,...,q28, 16 double precision d0,d2,d4,...,d30) +\item 32 32-bit integer/pointer registers out of a bigger (vendor/model dependent) number that are accessible at a time (8 are global ones (g*), whereas the remaining 24 form a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones) \item calling a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore) \end{itemize} \begin{table}[h] \begin{tabular*}{0.95\textwidth}{lll} -Name & Alias & Brief description\\ +Name & Alias & Brief description\\ \hline -{\bf \%g0} & & Read-only, hardwired to 0 \\ -{\bf \%g1-\%g7} & & Global \\ -{\bf \%o0 and \%i0} & & Output and input argument 0, return value \\ -{\bf \%o1-\%o5 and \%i1-\%i5} & & Output and input argument registers \\ -{\bf \%o6 and \%i6} & & Stack and frame pointer \\ -{\bf \%o7 and \%i7} & & Return address (caller writes to o7, callee uses i7) \\ +{\bf \%g0} & \%r0 & Read-only, hardwired to 0 \\ +{\bf \%g1-\%g7} & \%r1-\%r7 & Global \\ +{\bf \%o0,\%o1 and \%i0,\%i1} & \%r8,\%r9 and \%r24,\%r25 & Output and input argument registers, return value \\ +{\bf \%o2-\%o5 and \%i2-\%i5} & \%r10-\%r13 and \%r26-\%r29 & Output and input argument registers \\ +{\bf \%o6 and \%i6} & \%r14 and \%r30, \%sp and \%fp & Stack and frame pointer \\ +{\bf \%o7 and \%i7} & \%r15 and \%r31 & Return address (caller writes to o7, callee uses i7) \\ +{\bf \%l0-\%l7} & \%r16-\%r23 & preserve \\ +{\bf \%f0,\%f1} & & Floating point return value \\ +{\bf \%f2-\%f31} & & scratch \\ \end{tabular*} \caption{Register usage on sparc calling convention} \end{table} @@ -102,6 +104,6 @@ \\ \\ \\ -\caption{Stack layout on sparc calling convention} +\caption{Stack layout on sparc32 calling convention} \end{figure} diff -r 600bd90afdb7 -r 41d6945f5858 doc/manual/callconvs/callconv_sparc64.tex --- a/doc/manual/callconvs/callconv_sparc64.tex Tue Mar 14 03:25:12 2017 +0100 +++ b/doc/manual/callconvs/callconv_sparc64.tex Sat Mar 18 19:08:45 2017 +0100 @@ -24,6 +24,8 @@ The SPARC family of processors is based on the SPARC instruction set architecture, which comes in basically tree revisions, V7, V8\cite{SPARCV8}\cite{SPARCSysV} and V9\cite{SPARCV9}\cite{SPARCV9SysV}. The former two are 32-bit (see previous chapter) whereas the latter refers to the 64-bit SPARC architecture. SPARC uses big endian byte order, however, V9 supports also little endian byte order, but for data access only, not instruction access.\\ +\\ +There are two probosals, one from Sun and one from Hal, which disagree on how to handle some aspects of this calling convention.\\ \paragraph{\product{dyncall} support} @@ -31,4 +33,78 @@ \subsubsection{SPARC (64-bit) Calling Convention} -@@@ finish +\begin{itemize} +\item 32 double precision floating point registers (d0,d2,d4,...,d62, usable as 16 quad precision ones q0,q4,q8,...g60, and also first half of them are usable as 32 single precision registers f0-f31) +\item 32 64-bit integer/pointer registers out of a bigger (vendor/model dependent) number that are accessible at a time (8 are global ones (g*), whereas the remaining 24 form a register window with 8 input (i*), 8 output (o*) and 8 local (l*) ones) +\item calling a function shifts the register window, the old output registers become the new input registers (old local and input ones are not accessible anymore) +\item stack and frame pointer are offset by a BIAS of 2047 (see official doc for reasons) +\end{itemize} + +\begin{table}[h] +\begin{tabular*}{0.95\textwidth}{lll} +Name & Alias & Brief description\\ +\hline +{\bf \%g0} & \%r0 & Read-only, hardwired to 0 \\ +{\bf \%g1-\%g7} & \%r1-\%r7 & Global \\ +{\bf \%o0-\%o3 and \%i0-\%i3} & \%r8-\%r11 and \%r24-\%r27 & Output and input argument registers, return value \\ +{\bf \%o4,\%o5 and \%i4,\%i5} & \%r12,\%r13 and \%r28,\%r29 & Output and input argument registers \\ +{\bf \%o6 and \%i6} & \%r14 and \%r30, \%sp and \%fp & Stack and frame pointer (NOTE, value is pointing to stack/frame minus a BIAS of 2047) \\ +{\bf \%o7 and \%i7} & \%r15 and \%r31 & Return address (caller writes to o7, callee uses i7) \\ +{\bf \%l0-\%l7} & \%r16-\%r23 & preserve \\ +{\bf \%d0,\%d2,\%d4,\%d6} & & Floating point arguments, return value \\ +{\bf \%d8,\%d10,...,\%d30} & & Floating point arguments \\ +{\bf \%d32,\%d36,...,\%d62} & & scratch (but, according do Hal, \%d16,...,\%d46 are preserved) \\ +\end{tabular*} +\caption{Register usage on sparc64 calling convention} +\end{table} + +\paragraph{Parameter passing} +\begin{itemize} +\item stack grows down +\item stack parameter order: right-to-left +\item caller cleans up the stack +\item stack always aligned to 8 bytes +\item first 6 integers are passed in registers using \%o0-\%o5 +\item first 8 quad precision floating point args (or 16 double precision, or 32 single precision) are passed in floating point registers (\%q0,\%q4,...,\%q28 or \%d0,\%d2,...,\%d30 or \%f0-\%f32, respectively) +\item for every other argument the stack is used +\item for every floating point argument passed in a register, corresponding \%o* registers or stack space is skipped (e.g. if \%d0 is used for 3rd call argument, \%o2 is skipped and not used for subsequent integer arguments) +\item all arguments \textless=\ 64 bit are passed as 64 bit values +\item minimum stack size is 128 bytes, b/c stack pointer must always point at enough space to store all \%i* and \%l* registers, used when running out of register windows +\item if needed, register spill area (for integer arguments passed via \%o0-\%o5) is adjacent to parameters +\item results are expected by caller to be returned in \%o0-\%o3 (after reg window restore, meaning callee writes to \%i0-\%i3) for integers, \%d0,\%d2,\%d4,\%d6 for floats, and for structs/unions a pointer to them is used as a hidden stack parameter (see below) +\end{itemize} + +\paragraph{Stack layout} + +Stack directly after function prolog:\\ + +\begin{figure}[h] +\begin{tabular}{5|3|1 1} +\hhline{~-~~} + & \vdots & & \\ +\hhline{~=~~} +local data & \hspace{4cm} & & \mrrbrace{10}{caller's frame} \\ +\hhline{~-~~} +\mrlbrace{7}{parameter area} & argument x & \mrrbrace{3}{stack parameters} & \\ + & \ldots & & \\ + & argument 6 & & \\ + & input argument 5 spill & \mrrbrace{3}{spill area} & \\ + & \ldots & & \\ + & input argument 0 spill & & \\ + & struct/union return pointer & & \\ +\hhline{~-~~} +register save area (\%i* and \%l*) & & & \\ +\hhline{~=~~} +local data & & & \mrrbrace{3}{current frame} \\ +\hhline{~-~~} +parameter area & & & \\ +\hhline{~-~~} + & \vdots & & \\ +\hhline{~-~~} +\end{tabular} +\\ +\\ +\\ +\caption{Stack layout on sparc64 calling convention} +\end{figure} +