--- a/doc/manual/callconvs/callconv_sparc64.tex	Fri Feb 24 23:05:53 2017 +0100
+++ b/doc/manual/callconvs/callconv_sparc64.tex	Mon Mar 13 11:27:05 2017 +0100
@@ -1,7 +1,7 @@
 %//////////////////////////////////////////////////////////////////////////////
 %
-% Copyright (c) 2012 Daniel Adler <dadler@uni-goettingen.de>, 
-%                    Tassilo Philipp <tphilipp@potion-studios.com>
+% Copyright (c) 2012-2017 Daniel Adler <dadler@uni-goettingen.de>,
+%                         Tassilo Philipp <tphilipp@potion-studios.com>
 %
 % Permission to use, copy, modify, and distribute this software for any
 % purpose with or without fee is hereby granted, provided that the above
@@ -22,7 +22,8 @@
 \paragraph{Overview}
 
 The SPARC family of processors is based on the SPARC instruction set architecture, which comes in basically tree revisions,
-V7, V8 and V9. The former two are 32-bit (see previous chapter) whereas the latter refers to the 64-bit SPARC architecture. SPARC is big endian.\\
+V7, V8 and V9.\cite{SPARCRef} The former two are 32-bit (see previous chapter) whereas the latter refers to the 64-bit SPARC architecture.
+SPARC uses big endian byte order, however, V9 supports also little endian byte order, but for data access only, not instruction access.\cite{SPARCV9}\\
 
 \paragraph{\product{dyncall} support}