Mercurial > pub > dyncall > dyncall
diff doc/disas_examples/ppc.sysv.disas @ 327:c0390dc85a07
- doc: added disassembly examples for many platforms and calling conventions, for reference
| author | Tassilo Philipp |
|---|---|
| date | Fri, 22 Nov 2019 23:08:59 +0100 |
| parents | |
| children | 06c9adae114d |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/doc/disas_examples/ppc.sysv.disas Fri Nov 22 23:08:59 2019 +0100 @@ -0,0 +1,614 @@ +; #include <stdlib.h> +; +; void leaf_call(int b, int c, int d, int e, int f, int g, int h) +; { +; } +; +; void nonleaf_call(int a, int b, int c, int d, int e, int f, int g, int h) +; { +; /* use some local data */ +; *(char*)alloca(10) = 'L'; +; leaf_call(b, c, d, e, f, g, h); +; } +; +; int main() +; { +; nonleaf_call(0, 1, 2, 3, 4, 5, 6, 7); +; return 0; +; } + + + +; output from debian-4.1.1-21-ppc w/ gcc 4.1.2 + +00000000 <leaf_call>: + 0: 94 21 ff d0 stwu r1,-48(r1) + 4: 93 e1 00 2c stw r31,44(r1) + 8: 7c 3f 0b 78 mr r31,r1 + c: 90 7f 00 08 stw r3,8(r31) + 10: 90 9f 00 0c stw r4,12(r31) + 14: 90 bf 00 10 stw r5,16(r31) + 18: 90 df 00 14 stw r6,20(r31) + 1c: 90 ff 00 18 stw r7,24(r31) + 20: 91 1f 00 1c stw r8,28(r31) + 24: 91 3f 00 20 stw r9,32(r31) + 28: 81 61 00 00 lwz r11,0(r1) + 2c: 83 eb ff fc lwz r31,-4(r11) + 30: 7d 61 5b 78 mr r1,r11 + 34: 4e 80 00 20 blr + +00000038 <nonleaf_call>: + 38: 94 21 ff c0 stwu r1,-64(r1) ; | open frame and store sp at top of stack + 3c: 7c 08 02 a6 mflr r0 ; | lr -> gpr0 + 40: 93 e1 00 3c stw r31,60(r1) ; | prolog store gpr31 + 44: 90 01 00 44 stw r0,68(r1) ; | store lr + 48: 7c 3f 0b 78 mr r31,r1 ; / sp -> gpr31, latter used for some fixed addressing below + 4c: 90 7f 00 08 stw r3,8(r31) ; \ + 50: 90 9f 00 0c stw r4,12(r31) ; | + 54: 90 bf 00 10 stw r5,16(r31) ; | + 58: 90 df 00 14 stw r6,20(r31) ; | + 5c: 90 ff 00 18 stw r7,24(r31) ; | all in args -> temp space in local area + 60: 91 1f 00 1c stw r8,28(r31) ; | + 64: 91 3f 00 20 stw r9,32(r31) ; | + 68: 91 5f 00 24 stw r10,36(r31) ; | + 6c: 80 01 00 00 lwz r0,0(r1) ; fetch sp saved on stack of top by prolog -> gpr0, and ... + 70: 94 01 ff 10 stwu r0,-240(r1) ; ... update it further up the stack for alloca(220) - with padding to guarantee alignment + 74: 39 21 00 08 addi r9,r1,8 ; | + 78: 91 3f 00 28 stw r9,40(r31) ; | + 7c: 81 3f 00 28 lwz r9,40(r31) ; | + 80: 38 09 00 0f addi r0,r9,15 ; | start of alloca()'d memory -> gpr9, by ... + 84: 54 00 e1 3e rlwinm r0,r0,28,4,31 ; | ... using gpr0 as helper to align to 16b, leaving at least 8b at top of stock + 88: 54 00 20 36 rlwinm r0,r0,4,0,27 ; | + 8c: 90 1f 00 28 stw r0,40(r31) ; | + 90: 81 3f 00 28 lwz r9,40(r31) ; | + 94: 38 00 00 4c li r0,76 ; 'L' -> gpr0, and ... + 98: 98 09 00 00 stb r0,0(r9) ; ... store in local area (of alloca()'d space) + 9c: 80 7f 00 0c lwz r3,12(r31) ; arg 0 + a0: 80 9f 00 10 lwz r4,16(r31) ; arg 1 + a4: 80 bf 00 14 lwz r5,20(r31) ; arg 2 + a8: 80 df 00 18 lwz r6,24(r31) ; arg 3 + ac: 80 ff 00 1c lwz r7,28(r31) ; arg 4 + b0: 81 1f 00 20 lwz r8,32(r31) ; arg 5 + b4: 81 3f 00 24 lwz r9,36(r31) ; arg 6 + b8: 48 00 00 01 bl b8 <nonleaf_call+0x80> ; call and put return address -> lr + bc: 81 61 00 00 lwz r11,0(r1) ; | + c0: 80 0b 00 04 lwz r0,4(r11) ; | + c4: 7c 08 03 a6 mtlr r0 ; | + c8: 83 eb ff fc lwz r31,-4(r11) ; | epilog + cc: 7d 61 5b 78 mr r1,r11 ; | + d0: 4e 80 00 20 blr ; | + +000000d4 <main>: + d4: 94 21 ff f0 stwu r1,-16(r1) ; | + d8: 7c 08 02 a6 mflr r0 ; | + dc: 93 e1 00 0c stw r31,12(r1) ; | prolog + e0: 90 01 00 14 stw r0,20(r1) ; | + e4: 7c 3f 0b 78 mr r31,r1 ; | + e8: 38 60 00 00 li r3,0 ; arg 0 + ec: 38 80 00 01 li r4,1 ; arg 1 + f0: 38 a0 00 02 li r5,2 ; arg 2 + f4: 38 c0 00 03 li r6,3 ; arg 3 + f8: 38 e0 00 04 li r7,4 ; arg 4 + fc: 39 00 00 05 li r8,5 ; arg 5 + 100: 39 20 00 06 li r9,6 ; arg 6 + 104: 39 40 00 07 li r10,7 ; arg 7 + 108: 48 00 00 01 bl 108 <main+0x34> ; call and put return address -> lr + 10c: 38 00 00 00 li r0,0 ; return value (pointlessly) via gpr0 ... + 110: 7c 03 03 78 mr r3,r0 ; ... to gpr3 + 114: 81 61 00 00 lwz r11,0(r1) ; | + 118: 80 0b 00 04 lwz r0,4(r11) ; | + 11c: 7c 08 03 a6 mtlr r0 ; | + 120: 83 eb ff fc lwz r31,-4(r11) ; | epilog + 124: 7d 61 5b 78 mr r1,r11 ; | + 128: 4e 80 00 20 blr ; | + + + +; output from netbsd-4.0.1-macppc w/ gcc 4.1.2 + +00000000 <leaf_call>: + 0: 94 21 ff c0 stwu r1,-64(r1) + 4: 93 e1 00 3c stw r31,60(r1) + 8: 7c 3f 0b 78 mr r31,r1 + c: 90 7f 00 08 stw r3,8(r31) + 10: 90 9f 00 0c stw r4,12(r31) + 14: 90 bf 00 10 stw r5,16(r31) + 18: 90 df 00 14 stw r6,20(r31) + 1c: 90 ff 00 18 stw r7,24(r31) + 20: 91 1f 00 1c stw r8,28(r31) + 24: 91 3f 00 20 stw r9,32(r31) + 28: 81 61 00 00 lwz r11,0(r1) + 2c: 83 eb ff fc lwz r31,-4(r11) + 30: 7d 61 5b 78 mr r1,r11 + 34: 4e 80 00 20 blr + +00000038 <nonleaf_call>: + 38: 94 21 ff c0 stwu r1,-64(r1) + 3c: 7c 08 02 a6 mflr r0 + 40: 93 e1 00 3c stw r31,60(r1) + 44: 90 01 00 44 stw r0,68(r1) + 48: 7c 3f 0b 78 mr r31,r1 + 4c: 90 7f 00 08 stw r3,8(r31) + 50: 90 9f 00 0c stw r4,12(r31) + 54: 90 bf 00 10 stw r5,16(r31) + 58: 90 df 00 14 stw r6,20(r31) + 5c: 90 ff 00 18 stw r7,24(r31) + 60: 91 1f 00 1c stw r8,28(r31) + 64: 91 3f 00 20 stw r9,32(r31) + 68: 91 5f 00 24 stw r10,36(r31) + 6c: 80 01 00 00 lwz r0,0(r1) + 70: 94 01 ff 10 stwu r0,-240(r1) + 74: 39 21 00 08 addi r9,r1,8 + 78: 91 3f 00 28 stw r9,40(r31) + 7c: 81 3f 00 28 lwz r9,40(r31) + 80: 38 09 00 0f addi r0,r9,15 + 84: 54 00 e1 3e rlwinm r0,r0,28,4,31 + 88: 54 00 20 36 rlwinm r0,r0,4,0,27 + 8c: 90 1f 00 28 stw r0,40(r31) + 90: 81 3f 00 28 lwz r9,40(r31) + 94: 38 00 00 4c li r0,76 + 98: 98 09 00 00 stb r0,0(r9) + 9c: 80 7f 00 0c lwz r3,12(r31) + a0: 80 9f 00 10 lwz r4,16(r31) + a4: 80 bf 00 14 lwz r5,20(r31) + a8: 80 df 00 18 lwz r6,24(r31) + ac: 80 ff 00 1c lwz r7,28(r31) + b0: 81 1f 00 20 lwz r8,32(r31) + b4: 81 3f 00 24 lwz r9,36(r31) + b8: 48 00 00 01 bl b8 <nonleaf_call+0x80> + bc: 81 61 00 00 lwz r11,0(r1) + c0: 80 0b 00 04 lwz r0,4(r11) + c4: 7c 08 03 a6 mtlr r0 + c8: 83 eb ff fc lwz r31,-4(r11) + cc: 7d 61 5b 78 mr r1,r11 + d0: 4e 80 00 20 blr + +000000d4 <main>: + d4: 94 21 ff e0 stwu r1,-32(r1) + d8: 7c 08 02 a6 mflr r0 + dc: 93 e1 00 1c stw r31,28(r1) + e0: 90 01 00 24 stw r0,36(r1) + e4: 7c 3f 0b 78 mr r31,r1 + e8: 38 60 00 00 li r3,0 + ec: 38 80 00 01 li r4,1 + f0: 38 a0 00 02 li r5,2 + f4: 38 c0 00 03 li r6,3 + f8: 38 e0 00 04 li r7,4 + fc: 39 00 00 05 li r8,5 + 100: 39 20 00 06 li r9,6 + 104: 39 40 00 07 li r10,7 + 108: 48 00 00 01 bl 108 <main+0x34> + 10c: 38 00 00 00 li r0,0 + 110: 7c 03 03 78 mr r3,r0 + 114: 81 61 00 00 lwz r11,0(r1) + 118: 80 0b 00 04 lwz r0,4(r11) + 11c: 7c 08 03 a6 mtlr r0 + 120: 83 eb ff fc lwz r31,-4(r11) + 124: 7d 61 5b 78 mr r1,r11 + 128: 4e 80 00 20 blr + + + +; ------------- check register skipping for 64bit args -----------> + +; void call(int a, long long b, int c, int d, long long e, long long f) +; { +; } +; +; int main() +; { +; call(0,1,2,3,4,5); +; return 1; +; } + + + +; output from debian-4.1.1-21-ppc w/ gcc 4.1.2 + +00000000 <call>: + 0: 94 21 ff d0 stwu r1,-48(r1) + 4: 93 e1 00 2c stw r31,44(r1) + 8: 7c 3f 0b 78 mr r31,r1 + c: 90 7f 00 08 stw r3,8(r31) + 10: 90 bf 00 10 stw r5,16(r31) + 14: 90 df 00 14 stw r6,20(r31) + 18: 90 ff 00 18 stw r7,24(r31) + 1c: 91 1f 00 1c stw r8,28(r31) + 20: 91 3f 00 20 stw r9,32(r31) + 24: 91 5f 00 24 stw r10,36(r31) + 28: 81 61 00 00 lwz r11,0(r1) + 2c: 83 eb ff fc lwz r31,-4(r11) + 30: 7d 61 5b 78 mr r1,r11 + 34: 4e 80 00 20 blr + +00000038 <main>: + 38: 94 21 ff e0 stwu r1,-32(r1) ; | + 3c: 7c 08 02 a6 mflr r0 ; | + 40: 93 e1 00 1c stw r31,28(r1) ; | prolog + 44: 90 01 00 24 stw r0,36(r1) ; | + 48: 7c 3f 0b 78 mr r31,r1 ; / + 4c: 39 20 00 00 li r9,0 ; \ + 50: 39 40 00 05 li r10,5 ; | + 54: 91 21 00 08 stw r9,8(r1) ; | arg 5 via stack + 58: 91 41 00 0c stw r10,12(r1) ; | + 5c: 38 60 00 00 li r3,0 ; arg 0 + 60: 38 a0 00 00 li r5,0 ; | + 64: 38 c0 00 01 li r6,1 ; | arg 1 (note that r4 is skipped) + 68: 38 e0 00 02 li r7,2 ; arg 2 + 6c: 39 00 00 03 li r8,3 ; arg 3 + 70: 39 20 00 00 li r9,0 ; | + 74: 39 40 00 04 li r10,4 ; | arg 4 + 78: 48 00 00 01 bl 78 <main+0x40> ; call and put return address -> lr + 7c: 38 00 00 01 li r0,1 ; return value (pointlessly) via gpr0 ... + 80: 7c 03 03 78 mr r3,r0 ; ... to gpr3 + 84: 81 61 00 00 lwz r11,0(r1) ; | + 88: 80 0b 00 04 lwz r0,4(r11) ; | + 8c: 7c 08 03 a6 mtlr r0 ; | + 90: 83 eb ff fc lwz r31,-4(r11) ; | epilog + 94: 7d 61 5b 78 mr r1,r11 ; | + 98: 4e 80 00 20 blr ; | + + + +; ------------- var args with ints and floats to see spilling (which remains only int regs), b/c doubles are passed via them and floats are promoted to doubles in (...) -----------> + +; #include <stdlib.h> +; #include <stdarg.h> +; +; void leaf_call(int b, int c, int d, int e, float f, float g, int h, int i, float j) +; { +; } +; +; void nonleaf_call(int a, ...) +; { +; int b, c, d, e, h, i; +; float f, g, j; +; va_list ap; +; va_start(ap, a); +; b = va_arg(ap, int); +; c = va_arg(ap, int); +; d = va_arg(ap, int); +; e = va_arg(ap, int); +; f = (float)va_arg(ap, double); +; g = (float)va_arg(ap, double); +; h = va_arg(ap, int); +; i = va_arg(ap, int); +; j = (float)va_arg(ap, double); +; /* use some local data */ +; *(char*)alloca(220) = 'L'; +; leaf_call(b, c, d, e, f, g, h, i, j); +; } +; +; int main() +; { +; nonleaf_call(0, 1, 2, 3, 4, 5.f, 6.f, 7, 8, 9.f); +; return 0; +; } + + + +; output from debian-4.1.1-21-ppc w/ gcc 4.1.2 + +00000000 <leaf_call>: + 0: 94 21 ff c0 stwu r1,-64(r1) + 4: 93 e1 00 3c stw r31,60(r1) + 8: 7c 3f 0b 78 mr r31,r1 + c: 90 7f 00 08 stw r3,8(r31) + 10: 90 9f 00 0c stw r4,12(r31) + 14: 90 bf 00 10 stw r5,16(r31) + 18: 90 df 00 14 stw r6,20(r31) + 1c: d0 3f 00 18 stfs f1,24(r31) + 20: d0 5f 00 1c stfs f2,28(r31) + 24: 90 ff 00 20 stw r7,32(r31) + 28: 91 1f 00 24 stw r8,36(r31) + 2c: d0 7f 00 28 stfs f3,40(r31) + 30: 81 61 00 00 lwz r11,0(r1) + 34: 83 eb ff fc lwz r31,-4(r11) + 38: 7d 61 5b 78 mr r1,r11 + 3c: 4e 80 00 20 blr + +00000040 <nonleaf_call>: + 40: 94 21 ff 30 stwu r1,-208(r1) + 44: 7c 08 02 a6 mflr r0 + 48: 93 e1 00 cc stw r31,204(r1) + 4c: 90 01 00 d4 stw r0,212(r1) + 50: 7c 3f 0b 78 mr r31,r1 + 54: 90 9f 00 3c stw r4,60(r31) + 58: 90 bf 00 40 stw r5,64(r31) + 5c: 90 df 00 44 stw r6,68(r31) + 60: 90 ff 00 48 stw r7,72(r31) + 64: 91 1f 00 4c stw r8,76(r31) + 68: 91 3f 00 50 stw r9,80(r31) + 6c: 91 5f 00 54 stw r10,84(r31) + 70: 40 86 00 24 bne- cr1,94 <nonleaf_call+0x54> + 74: d8 3f 00 58 stfd f1,88(r31) + 78: d8 5f 00 60 stfd f2,96(r31) + 7c: d8 7f 00 68 stfd f3,104(r31) + 80: d8 9f 00 70 stfd f4,112(r31) + 84: d8 bf 00 78 stfd f5,120(r31) + 88: d8 df 00 80 stfd f6,128(r31) + 8c: d8 ff 00 88 stfd f7,136(r31) + 90: d9 1f 00 90 stfd f8,144(r31) + 94: 90 7f 00 98 stw r3,152(r31) + 98: 38 00 00 01 li r0,1 + 9c: 98 1f 00 2c stb r0,44(r31) + a0: 38 00 00 00 li r0,0 + a4: 98 1f 00 2d stb r0,45(r31) + a8: 38 1f 00 d8 addi r0,r31,216 ; make r0 point to start of prev frame's param area (would make sense as no spill area to define param area start for iteration) + ac: 90 1f 00 30 stw r0,48(r31) + b0: 38 1f 00 38 addi r0,r31,56 ; make r0 point to end of prev frame's param area (would make sense as no spill area to define param area end for iteration) + b4: 90 1f 00 34 stw r0,52(r31) + b8: 88 1f 00 2c lbz r0,44(r31) + bc: 54 00 06 3e clrlwi r0,r0,24 + c0: 2b 80 00 08 cmplwi cr7,r0,8 + c4: 40 9c 00 30 bge- cr7,f4 <nonleaf_call+0xb4> + c8: 81 7f 00 34 lwz r11,52(r31) + cc: 88 1f 00 2c lbz r0,44(r31) + d0: 54 09 06 3e clrlwi r9,r0,24 + d4: 7d 20 4b 78 mr r0,r9 + d8: 54 00 10 3a rlwinm r0,r0,2,0,29 + dc: 7d 6b 02 14 add r11,r11,r0 + e0: 91 7f 00 c0 stw r11,192(r31) + e4: 38 09 00 01 addi r0,r9,1 + e8: 54 00 06 3e clrlwi r0,r0,24 + ec: 98 1f 00 2c stb r0,44(r31) + f0: 48 00 00 14 b 104 <nonleaf_call+0xc4> + f4: 81 3f 00 30 lwz r9,48(r31) + f8: 91 3f 00 c0 stw r9,192(r31) + fc: 38 09 00 04 addi r0,r9,4 + 100: 90 1f 00 30 stw r0,48(r31) + 104: 81 3f 00 c0 lwz r9,192(r31) + 108: 80 09 00 00 lwz r0,0(r9) + 10c: 90 1f 00 28 stw r0,40(r31) + 110: 88 1f 00 2c lbz r0,44(r31) + 114: 54 00 06 3e clrlwi r0,r0,24 + 118: 2b 80 00 08 cmplwi cr7,r0,8 + 11c: 40 9c 00 30 bge- cr7,14c <nonleaf_call+0x10c> + 120: 81 7f 00 34 lwz r11,52(r31) + 124: 88 1f 00 2c lbz r0,44(r31) + 128: 54 09 06 3e clrlwi r9,r0,24 + 12c: 7d 20 4b 78 mr r0,r9 + 130: 54 00 10 3a rlwinm r0,r0,2,0,29 + 134: 7d 6b 02 14 add r11,r11,r0 + 138: 91 7f 00 bc stw r11,188(r31) + 13c: 38 09 00 01 addi r0,r9,1 + 140: 54 00 06 3e clrlwi r0,r0,24 + 144: 98 1f 00 2c stb r0,44(r31) + 148: 48 00 00 14 b 15c <nonleaf_call+0x11c> + 14c: 81 3f 00 30 lwz r9,48(r31) + 150: 91 3f 00 bc stw r9,188(r31) + 154: 38 09 00 04 addi r0,r9,4 + 158: 90 1f 00 30 stw r0,48(r31) + 15c: 81 3f 00 bc lwz r9,188(r31) + 160: 80 09 00 00 lwz r0,0(r9) + 164: 90 1f 00 24 stw r0,36(r31) + 168: 88 1f 00 2c lbz r0,44(r31) + 16c: 54 00 06 3e clrlwi r0,r0,24 + 170: 2b 80 00 08 cmplwi cr7,r0,8 + 174: 40 9c 00 30 bge- cr7,1a4 <nonleaf_call+0x164> + 178: 81 7f 00 34 lwz r11,52(r31) + 17c: 88 1f 00 2c lbz r0,44(r31) + 180: 54 09 06 3e clrlwi r9,r0,24 + 184: 7d 20 4b 78 mr r0,r9 + 188: 54 00 10 3a rlwinm r0,r0,2,0,29 + 18c: 7d 6b 02 14 add r11,r11,r0 + 190: 91 7f 00 b8 stw r11,184(r31) + 194: 38 09 00 01 addi r0,r9,1 + 198: 54 00 06 3e clrlwi r0,r0,24 + 19c: 98 1f 00 2c stb r0,44(r31) + 1a0: 48 00 00 14 b 1b4 <nonleaf_call+0x174> + 1a4: 81 3f 00 30 lwz r9,48(r31) + 1a8: 91 3f 00 b8 stw r9,184(r31) + 1ac: 38 09 00 04 addi r0,r9,4 + 1b0: 90 1f 00 30 stw r0,48(r31) + 1b4: 81 3f 00 b8 lwz r9,184(r31) + 1b8: 80 09 00 00 lwz r0,0(r9) + 1bc: 90 1f 00 20 stw r0,32(r31) + 1c0: 88 1f 00 2c lbz r0,44(r31) + 1c4: 54 00 06 3e clrlwi r0,r0,24 + 1c8: 2b 80 00 08 cmplwi cr7,r0,8 + 1cc: 40 9c 00 30 bge- cr7,1fc <nonleaf_call+0x1bc> + 1d0: 81 7f 00 34 lwz r11,52(r31) + 1d4: 88 1f 00 2c lbz r0,44(r31) + 1d8: 54 09 06 3e clrlwi r9,r0,24 + 1dc: 7d 20 4b 78 mr r0,r9 + 1e0: 54 00 10 3a rlwinm r0,r0,2,0,29 + 1e4: 7d 6b 02 14 add r11,r11,r0 + 1e8: 91 7f 00 b4 stw r11,180(r31) + 1ec: 38 09 00 01 addi r0,r9,1 + 1f0: 54 00 06 3e clrlwi r0,r0,24 + 1f4: 98 1f 00 2c stb r0,44(r31) + 1f8: 48 00 00 14 b 20c <nonleaf_call+0x1cc> + 1fc: 81 3f 00 30 lwz r9,48(r31) + 200: 91 3f 00 b4 stw r9,180(r31) + 204: 38 09 00 04 addi r0,r9,4 + 208: 90 1f 00 30 stw r0,48(r31) + 20c: 81 3f 00 b4 lwz r9,180(r31) + 210: 80 09 00 00 lwz r0,0(r9) + 214: 90 1f 00 1c stw r0,28(r31) + 218: 88 1f 00 2d lbz r0,45(r31) + 21c: 54 00 06 3e clrlwi r0,r0,24 + 220: 2b 80 00 08 cmplwi cr7,r0,8 + 224: 40 9c 00 34 bge- cr7,258 <nonleaf_call+0x218> + 228: 81 3f 00 34 lwz r9,52(r31) + 22c: 39 69 00 20 addi r11,r9,32 + 230: 88 1f 00 2d lbz r0,45(r31) + 234: 54 09 06 3e clrlwi r9,r0,24 + 238: 7d 20 4b 78 mr r0,r9 + 23c: 54 00 18 38 rlwinm r0,r0,3,0,28 + 240: 7d 6b 02 14 add r11,r11,r0 + 244: 91 7f 00 b0 stw r11,176(r31) + 248: 38 09 00 01 addi r0,r9,1 + 24c: 54 00 06 3e clrlwi r0,r0,24 + 250: 98 1f 00 2d stb r0,45(r31) + 254: 48 00 00 1c b 270 <nonleaf_call+0x230> + 258: 81 3f 00 30 lwz r9,48(r31) + 25c: 38 09 00 07 addi r0,r9,7 + 260: 54 09 00 38 rlwinm r9,r0,0,0,28 + 264: 91 3f 00 b0 stw r9,176(r31) + 268: 38 09 00 08 addi r0,r9,8 + 26c: 90 1f 00 30 stw r0,48(r31) + 270: 81 3f 00 b0 lwz r9,176(r31) + 274: c8 09 00 00 lfd f0,0(r9) + 278: fc 00 00 18 frsp f0,f0 + 27c: d0 1f 00 10 stfs f0,16(r31) + 280: 88 1f 00 2d lbz r0,45(r31) + 284: 54 00 06 3e clrlwi r0,r0,24 + 288: 2b 80 00 08 cmplwi cr7,r0,8 + 28c: 40 9c 00 34 bge- cr7,2c0 <nonleaf_call+0x280> + 290: 81 3f 00 34 lwz r9,52(r31) + 294: 39 69 00 20 addi r11,r9,32 + 298: 88 1f 00 2d lbz r0,45(r31) + 29c: 54 09 06 3e clrlwi r9,r0,24 + 2a0: 7d 20 4b 78 mr r0,r9 + 2a4: 54 00 18 38 rlwinm r0,r0,3,0,28 + 2a8: 7d 6b 02 14 add r11,r11,r0 + 2ac: 91 7f 00 ac stw r11,172(r31) + 2b0: 38 09 00 01 addi r0,r9,1 + 2b4: 54 00 06 3e clrlwi r0,r0,24 + 2b8: 98 1f 00 2d stb r0,45(r31) + 2bc: 48 00 00 1c b 2d8 <nonleaf_call+0x298> + 2c0: 81 3f 00 30 lwz r9,48(r31) + 2c4: 38 09 00 07 addi r0,r9,7 + 2c8: 54 09 00 38 rlwinm r9,r0,0,0,28 + 2cc: 91 3f 00 ac stw r9,172(r31) + 2d0: 38 09 00 08 addi r0,r9,8 + 2d4: 90 1f 00 30 stw r0,48(r31) + 2d8: 81 3f 00 ac lwz r9,172(r31) + 2dc: c8 09 00 00 lfd f0,0(r9) + 2e0: fc 00 00 18 frsp f0,f0 + 2e4: d0 1f 00 0c stfs f0,12(r31) + 2e8: 88 1f 00 2c lbz r0,44(r31) + 2ec: 54 00 06 3e clrlwi r0,r0,24 + 2f0: 2b 80 00 08 cmplwi cr7,r0,8 + 2f4: 40 9c 00 30 bge- cr7,324 <nonleaf_call+0x2e4> + 2f8: 81 7f 00 34 lwz r11,52(r31) + 2fc: 88 1f 00 2c lbz r0,44(r31) + 300: 54 09 06 3e clrlwi r9,r0,24 + 304: 7d 20 4b 78 mr r0,r9 + 308: 54 00 10 3a rlwinm r0,r0,2,0,29 + 30c: 7d 6b 02 14 add r11,r11,r0 + 310: 91 7f 00 a8 stw r11,168(r31) + 314: 38 09 00 01 addi r0,r9,1 + 318: 54 00 06 3e clrlwi r0,r0,24 + 31c: 98 1f 00 2c stb r0,44(r31) + 320: 48 00 00 14 b 334 <nonleaf_call+0x2f4> + 324: 81 3f 00 30 lwz r9,48(r31) + 328: 91 3f 00 a8 stw r9,168(r31) + 32c: 38 09 00 04 addi r0,r9,4 + 330: 90 1f 00 30 stw r0,48(r31) + 334: 81 3f 00 a8 lwz r9,168(r31) + 338: 80 09 00 00 lwz r0,0(r9) + 33c: 90 1f 00 18 stw r0,24(r31) + 340: 88 1f 00 2c lbz r0,44(r31) + 344: 54 00 06 3e clrlwi r0,r0,24 + 348: 2b 80 00 08 cmplwi cr7,r0,8 + 34c: 40 9c 00 30 bge- cr7,37c <nonleaf_call+0x33c> + 350: 81 7f 00 34 lwz r11,52(r31) + 354: 88 1f 00 2c lbz r0,44(r31) + 358: 54 09 06 3e clrlwi r9,r0,24 + 35c: 7d 20 4b 78 mr r0,r9 + 360: 54 00 10 3a rlwinm r0,r0,2,0,29 + 364: 7d 6b 02 14 add r11,r11,r0 + 368: 91 7f 00 a4 stw r11,164(r31) + 36c: 38 09 00 01 addi r0,r9,1 + 370: 54 00 06 3e clrlwi r0,r0,24 + 374: 98 1f 00 2c stb r0,44(r31) + 378: 48 00 00 14 b 38c <nonleaf_call+0x34c> + 37c: 81 3f 00 30 lwz r9,48(r31) + 380: 91 3f 00 a4 stw r9,164(r31) + 384: 38 09 00 04 addi r0,r9,4 + 388: 90 1f 00 30 stw r0,48(r31) + 38c: 81 3f 00 a4 lwz r9,164(r31) + 390: 80 09 00 00 lwz r0,0(r9) + 394: 90 1f 00 14 stw r0,20(r31) + 398: 88 1f 00 2d lbz r0,45(r31) + 39c: 54 00 06 3e clrlwi r0,r0,24 + 3a0: 2b 80 00 08 cmplwi cr7,r0,8 + 3a4: 40 9c 00 34 bge- cr7,3d8 <nonleaf_call+0x398> + 3a8: 81 3f 00 34 lwz r9,52(r31) + 3ac: 39 69 00 20 addi r11,r9,32 + 3b0: 88 1f 00 2d lbz r0,45(r31) + 3b4: 54 09 06 3e clrlwi r9,r0,24 + 3b8: 7d 20 4b 78 mr r0,r9 + 3bc: 54 00 18 38 rlwinm r0,r0,3,0,28 + 3c0: 7d 6b 02 14 add r11,r11,r0 + 3c4: 91 7f 00 a0 stw r11,160(r31) + 3c8: 38 09 00 01 addi r0,r9,1 + 3cc: 54 00 06 3e clrlwi r0,r0,24 + 3d0: 98 1f 00 2d stb r0,45(r31) + 3d4: 48 00 00 1c b 3f0 <nonleaf_call+0x3b0> + 3d8: 81 3f 00 30 lwz r9,48(r31) + 3dc: 38 09 00 07 addi r0,r9,7 + 3e0: 54 09 00 38 rlwinm r9,r0,0,0,28 + 3e4: 91 3f 00 a0 stw r9,160(r31) + 3e8: 38 09 00 08 addi r0,r9,8 + 3ec: 90 1f 00 30 stw r0,48(r31) + 3f0: 81 3f 00 a0 lwz r9,160(r31) + 3f4: c8 09 00 00 lfd f0,0(r9) + 3f8: fc 00 00 18 frsp f0,f0 + 3fc: d0 1f 00 08 stfs f0,8(r31) + 400: 80 01 00 00 lwz r0,0(r1) + 404: 94 01 ff 10 stwu r0,-240(r1) + 408: 39 21 00 08 addi r9,r1,8 + 40c: 91 3f 00 9c stw r9,156(r31) + 410: 81 3f 00 9c lwz r9,156(r31) + 414: 38 09 00 0f addi r0,r9,15 + 418: 54 00 e1 3e rlwinm r0,r0,28,4,31 + 41c: 54 00 20 36 rlwinm r0,r0,4,0,27 + 420: 90 1f 00 9c stw r0,156(r31) + 424: 81 3f 00 9c lwz r9,156(r31) + 428: 38 00 00 4c li r0,76 + 42c: 98 09 00 00 stb r0,0(r9) + 430: 80 7f 00 28 lwz r3,40(r31) + 434: 80 9f 00 24 lwz r4,36(r31) + 438: 80 bf 00 20 lwz r5,32(r31) + 43c: 80 df 00 1c lwz r6,28(r31) + 440: c0 3f 00 10 lfs f1,16(r31) + 444: c0 5f 00 0c lfs f2,12(r31) + 448: 80 ff 00 18 lwz r7,24(r31) + 44c: 81 1f 00 14 lwz r8,20(r31) + 450: c0 7f 00 08 lfs f3,8(r31) + 454: 48 00 00 01 bl 454 <nonleaf_call+0x414> + 458: 81 61 00 00 lwz r11,0(r1) + 45c: 80 0b 00 04 lwz r0,4(r11) + 460: 7c 08 03 a6 mtlr r0 + 464: 83 eb ff fc lwz r31,-4(r11) + 468: 7d 61 5b 78 mr r1,r11 + 46c: 4e 80 00 20 blr + +00000470 <main>: + 470: 94 21 ff f0 stwu r1,-16(r1) ; | + 474: 7c 08 02 a6 mflr r0 ; | + 478: 93 e1 00 0c stw r31,12(r1) ; | prolog + 47c: 90 01 00 14 stw r0,20(r1) ; | + 480: 7c 3f 0b 78 mr r31,r1 ; / + 484: 3d 20 00 00 lis r9,0 ; \ prep arg 5 (float, but double in reg & ellipsis), load from 0 b/c objdump is from .o, not finally linked exec + 488: c8 09 00 00 lfd f0,0(r9) ; / + 48c: 3d 20 00 00 lis r9,0 ; \ prep arg 6 (float, but double in reg & ellipsis), load from 0 b/c objdump is from .o, not finally linked exec + 490: c9 a9 00 08 lfd f13,8(r9) ; / + 494: 3d 20 00 00 lis r9,0 ; \ prep arg 9 (float, but double in reg & ellipsis), load from 0 b/c objdump is from .o, not finally linked exec + 498: c9 89 00 10 lfd f12,16(r9) ; / + 49c: 38 60 00 00 li r3,0 ; arg 0 + 4a0: 38 80 00 01 li r4,1 ; arg 1 + 4a4: 38 a0 00 02 li r5,2 ; arg 2 + 4a8: 38 c0 00 03 li r6,3 ; arg 3 + 4ac: 38 e0 00 04 li r7,4 ; arg 4 + 4b0: fc 20 00 90 fmr f1,f0 ; arg 5 + 4b4: fc 40 68 90 fmr f2,f13 ; arg 6 + 4b8: 39 00 00 07 li r8,7 ; arg 7 + 4bc: 39 20 00 08 li r9,8 ; arg 8 + 4c0: fc 60 60 90 fmr f3,f12 ; arg 9 + 4c4: 4c c6 32 42 crset 4*cr1+eq ; set CR bit for ellipse call + 4c8: 48 00 00 01 bl 4c8 <main+0x58> ; call and put return address -> lr + 4cc: 38 00 00 00 li r0,0 ; return value (pointlessly) via gpr0 ... + 4d0: 7c 03 03 78 mr r3,r0 ; ... to gpr3 + 4d4: 81 61 00 00 lwz r11,0(r1) ; | + 4d8: 80 0b 00 04 lwz r0,4(r11) ; | + 4dc: 7c 08 03 a6 mtlr r0 ; | + 4e0: 83 eb ff fc lwz r31,-4(r11) ; | epilog + 4e4: 7d 61 5b 78 mr r1,r11 ; | + 4e8: 4e 80 00 20 blr ; | + +; vim: ft=asm68k +