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comparison doc/manual/callconvs/callconv_mips64.tex @ 336:3c6bc720bc1f r1.1-RC1

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- doc: added mips64/n32 stub
author Tassilo Philipp
date Sat, 30 Nov 2019 15:57:28 +0100
parents 276eb8c87aa0
children 75c19f11b86a
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335:5fe52b7c6e02 336:3c6bc720bc1f
19 19
20 \subsection{MIPS64 Calling Conventions} 20 \subsection{MIPS64 Calling Conventions}
21 21
22 \paragraph{Overview} 22 \paragraph{Overview}
23 23
24 There are two main ABIs in use for MIPS64 chips, \emph{N64}\cite{MIPSn32/n64} and \emph{N32}\cite{MIPSn32/n64}. Both are 24 There are two main ABIs in use for MIPS64 chips, \emph{N64}\cite{MIPSn32/n64}
25 basically the same, except that N32 uses 32-bit pointers and long integers, instead of 64. All registers of a MIPS64 chip are considered 25 and \emph{N32}\cite{MIPSn32/n64}. Both are basically the same, except that N32
26 to be 64-bit wide, even for the N32 calling convention.\\ 26 uses ILP32 as programming model (32-bit pointers and long integers), whereas
27 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due to historical reasons (terminology didn't change from MIPS32).\\ 27 N64 uses LP64 (64-bit pointers and long integers). All registers of a MIPS64
28 Other than that there are correspoding 64-bit versions other MIPS32 ABIs, e.g. the EABI\cite{MIPSeabi} and O64\cite{MIPSo64}. 28 chip are considered to be 64-bit wide, even for the N32 calling convention.\\
29 The word size is defined to be 32 bits, a dword 64 bits. Note that this is due
30 to historical reasons (terminology didn't change from MIPS32).\\
31 Other than that there are correspoding 64-bit versions other MIPS32 ABIs, e.g.
32 the EABI\cite{MIPSeabi} and O64\cite{MIPSo64}.
29 33
30 \paragraph{\product{dyncall} support} 34 \paragraph{\product{dyncall} support}
31 35
32 For MIPS 64-bit machines, dyncall supports the N64 calling conventions for calls and callbacks (for all four combinations of big/little-endian, and soft/hard-float targets). 36 For MIPS 64-bit machines, dyncall supports the N64 calling conventions for calls and callbacks (for all four combinations of big/little-endian, and soft/hard-float targets).
33 The N32 calling convention might work - it used to, but hasn't been tested, recently. 37 The N32 calling convention might work - it used to, but hasn't been tested, recently.
36 40
37 \paragraph{Register usage} 41 \paragraph{Register usage}
38 42
39 \begin{table}[h] 43 \begin{table}[h]
40 \begin{tabular*}{0.95\textwidth}{lll} 44 \begin{tabular*}{0.95\textwidth}{lll}
41 Name & Alias & Brief description\\ 45 Name & Alias & Brief description\\
42 \hline 46 \hline
43 {\bf \$0} & {\bf \$zero} & hardware zero \\ 47 {\bf \$0} & {\bf \$zero} & hardware zero \\
44 {\bf \$1} & {\bf \$at} & assembler temporary, scratch \\ 48 {\bf \$1} & {\bf \$at} & assembler temporary, scratch \\
45 {\bf \$2-\$3} & {\bf \$v0-\$v1} & return value (only integer on hard-float targets), scratch \\ 49 {\bf \$2-\$3} & {\bf \$v0-\$v1} & return value (only integer on hard-float targets), scratch \\
46 {\bf \$4-\$11} & {\bf \$a0-\$a7} & first arguments (only integer on hard-float targets), scratch \\ 50 {\bf \$4-\$11} & {\bf \$a0-\$a7} & first arguments (only integer on hard-float targets), scratch \\
47 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & temporaries, scratch \\ 51 {\bf \$12-\$15,\$24} & {\bf \$t4-\$t7,\$t8} & temporaries, scratch \\
48 {\bf \$25} & {\bf \$t9} & temporary, address callee for all PIC calls (by convention), scratch \\ 52 {\bf \$25} & {\bf \$t9} & temporary, address callee for all PIC calls (by convention), scratch \\
49 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserve \\ 53 {\bf \$16-\$23} & {\bf \$s0-\$s7} & preserve \\
50 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & reserved for kernel \\ 54 {\bf \$26,\$27} & {\bf \$kt0,\$kt1} & reserved for kernel \\
51 {\bf \$28} & {\bf \$gp} & global pointer, preserve \\ 55 {\bf \$28} & {\bf \$gp} & global pointer, preserve \\
52 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\ 56 {\bf \$29} & {\bf \$sp} & stack pointer, preserve \\
53 {\bf \$30} & {\bf \$s8} & frame pointer, preserve \\ 57 {\bf \$30} & {\bf \$s8} & frame pointer, preserve \\
54 {\bf \$31} & {\bf \$ra} & return address, preserve \\ 58 {\bf \$31} & {\bf \$ra} & return address, preserve \\
55 {\bf hi, lo} & & multiply/divide special registers \\ 59 {\bf hi, lo} & & multiply/divide special registers \\
56 {\bf \$f0,\$f2} & & only on hard-float targets: float results, scratch \\ 60 {\bf \$f0,\$f2} & & only on hard-float targets: float results, scratch \\
57 {\bf \$f1,\$f3,\$f4-\$f11,\$f20-\$f23} & & only on hard-float targets: float temporaries, scratch \\ 61 {\bf \$f1,\$f3,\$f4-\$f11} & & only on hard-float targets: float temporaries, scratch \\
58 {\bf \$f12-\$f19} & & only on hard-float targets: float arguments, scratch \\ 62 {\bf \$f12-\$f19} & & only on hard-float targets: float arguments, scratch \\
59 {\bf \$f24-\$f31} & & only on hard-float targets: preserved \\%@@@on N32, this changes 63 {\bf \$f20-\$f23} & & only on hard-float targets: float temporaries, scratch \\
64 {\bf \$f24-\$f31} & & only on hard-float targets: preserved \\
60 \end{tabular*} 65 \end{tabular*}
61 \caption{Register usage on MIPS N64 calling convention} 66 \caption{Register usage on MIPS N64 calling convention}
62 \end{table} 67 \end{table}
63 68
64 \paragraph{Parameter passing} 69 \paragraph{Parameter passing}
77 \item only on hard-float targets: floating point results are returned in \$f0 82 \item only on hard-float targets: floating point results are returned in \$f0
78 \item if the callee takes the address of one of the parameters and uses it to address other unnamed parameters (e.g. varargs) it has to copy - in its prolog - the the argument registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed integer parameters require saving, though) % @@@ seems to *ONLY* spill with varargs, never for any other reason 83 \item if the callee takes the address of one of the parameters and uses it to address other unnamed parameters (e.g. varargs) it has to copy - in its prolog - the the argument registers to a reserved stack area adjacent to the other parameters on the stack (only the unnamed integer parameters require saving, though) % @@@ seems to *ONLY* spill with varargs, never for any other reason
79 \item float arguments passed in the variable part of a vararg call are passed like integers, meaning float registers don't ever need to be saved that way, so only \$a0-\$a7 are need to be spilled 84 \item float arguments passed in the variable part of a vararg call are passed like integers, meaning float registers don't ever need to be saved that way, so only \$a0-\$a7 are need to be spilled
80 \item quad precision float arguments are passed in even-odd register pairs, skipping one register if needed 85 \item quad precision float arguments are passed in even-odd register pairs, skipping one register if needed
81 \item integer parameters \textless\ 64 bit are right-justified (meaning occupy higher-address bytes) in their 8-byte slot on the stack, requiring extra-care for big-endian targets 86 \item integer parameters \textless\ 64 bit are right-justified (meaning occupy higher-address bytes) in their 8-byte slot on the stack, requiring extra-care for big-endian targets
82 \item single precision float parameters (32 bit) are left-justified in their 8-byte slot on the stack, but are right justified in fp-registers on big endian targets, as they aren't promoted @@@doc says "undecided", but openbsd/octeon(mipseb) has it as described here 87 \item single precision float parameters (32 bit) are left-justified in their 8-byte slot on the stack, but are right justified in fp-registers on big endian targets, as they aren't promoted (actually, official docs says "undecided", but real world implementations seem to use what is described here)
83 \end{itemize} 88 \end{itemize}
84 % maybe note somewhere that "prolog-based" spilling is neat for dyncall, as we don't have to care 89 % maybe note somewhere that "prolog-based" spilling is neat for dyncall, as we don't have to care
85 90
86 \paragraph{Stack layout} 91 \paragraph{Stack layout}
87 92
114 \end{figure} 119 \end{figure}
115 120
116 121
117 \subsubsection{MIPS N32 Calling Convention} 122 \subsubsection{MIPS N32 Calling Convention}
118 123
119 @@@ 124 Despite what one might think given the name, this is a MIPS 64-bit calling
125 convention. As mentioned in the overview of this chapter, it is nearly
126 identical to the N64 one, the differences being:
120 127
128 \begin{itemize}
129 \item uses ILP32 as programming model instead of LP64
130 \item floating point registers \$f20-\$f23 are to be preserved
131 \end{itemize}
132