comparison doc/manual/callconvs/callconv_x64.tex @ 328:276eb8c87aa0

- review and fixes, cleanup, amendments to calling convention appendix of manual
author Tassilo Philipp
date Fri, 22 Nov 2019 23:11:56 +0100
parents 277fe1ff3e14
children 74c056b597b7
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327:c0390dc85a07 328:276eb8c87aa0
1 %////////////////////////////////////////////////////////////////////////////// 1 %//////////////////////////////////////////////////////////////////////////////
2 % 2 %
3 % Copyright (c) 2007,2009 Daniel Adler <dadler@uni-goettingen.de>, 3 % Copyright (c) 2007-2019 Daniel Adler <dadler@uni-goettingen.de>,
4 % Tassilo Philipp <tphilipp@potion-studios.com> 4 % Tassilo Philipp <tphilipp@potion-studios.com>
5 % 5 %
6 % Permission to use, copy, modify, and distribute this software for any 6 % Permission to use, copy, modify, and distribute this software for any
7 % purpose with or without fee is hereby granted, provided that the above 7 % purpose with or without fee is hereby granted, provided that the above
8 % copyright notice and this permission notice appear in all copies. 8 % copyright notice and this permission notice appear in all copies.
18 %////////////////////////////////////////////////////////////////////////////// 18 %//////////////////////////////////////////////////////////////////////////////
19 19
20 % ================================================== 20 % ==================================================
21 % x64 21 % x64
22 % ================================================== 22 % ==================================================
23 \subsection{x64 Calling Convention} 23 \subsection{x64 Calling Conventions}
24 24
25 25
26 \paragraph{Overview} 26 \paragraph{Overview}
27 27
28 The x64 (64bit) architecture designed by AMD is based on Intel's x86 (32bit) 28 The x64 (64bit) architecture designed by AMD is based on Intel's x86 (32bit)
82 82
83 \begin{itemize} 83 \begin{itemize}
84 \item stack parameter order: right-to-left 84 \item stack parameter order: right-to-left
85 \item caller cleans up the stack 85 \item caller cleans up the stack
86 \item first 4 integer/pointer parameters are passed via rcx, rdx, r8, r9 (from left to right), others are pushed on stack (there is a 86 \item first 4 integer/pointer parameters are passed via rcx, rdx, r8, r9 (from left to right), others are pushed on stack (there is a
87 preserve area for the first 4) 87 spill area for the first 4)
88 \item float and double parameters are passed via xmm0l-xmm3l 88 \item float and double parameters are passed via xmm0l-xmm3l
89 \item first 4 parameters are passed via the correct register depending on the parameter type - with mixed float and int parameters, 89 \item first 4 parameters are passed via the correct register depending on the parameter type - with mixed float and int parameters,
90 some registers are left out (e.g. first parameter ends up in rcx or xmm0, second in rdx or xmm1, etc.) 90 some registers are left out (e.g. first parameter ends up in rcx or xmm0, second in rdx or xmm1, etc.)
91 \item parameters in registers are right justified 91 \item parameters in registers are right justified
92 \item parameters \textless\ 64bits are not zero extended - zero the upper bits contiaining garbage if needed (but they are always 92 \item parameters \textless\ 64bits are not zero extended - zero the upper bits contiaining garbage if needed (but they are always
112 \end{itemize} 112 \end{itemize}
113 113
114 114
115 \paragraph{Stack layout} 115 \paragraph{Stack layout}
116 116
117 Stack frame is always 16-byte aligned. Stack directly after function prolog:\\ 117 Stack frame is always 16-byte aligned.
118 % verified/amended: TP nov 2019 (@@@ no doc/disas_examples/x64.win.disas, yet...@@@)
119 Stack directly after function prolog:\\
118 120
119 \begin{figure}[h] 121 \begin{figure}[h]
120 \begin{tabular}{5|3|1 1} 122 \begin{tabular}{5|3|1 1}
121 \hhline{~-~~} 123 & \vdots & & \\
122 & \vdots & & \\ 124 \hhline{~=~~}
123 \hhline{~=~~} 125 register save area & \hspace{4cm} & & \mrrbrace{10}{caller's frame} \\
124 local data & \hspace{4cm} & & \mrrbrace{9}{caller's frame} \\ 126 \hhline{~-~~}
125 \hhline{~-~~} 127 local data & & & \\
126 \mrlbrace{7}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ 128 \hhline{~-~~}
127 & \ldots & & \\ 129 \mrlbrace{7}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\
128 & \ldots & & \\ 130 & \ldots & & \\
129 & r9 or xmm3 & \mrrbrace{4}{spill area} & \\ 131 & arg 4 & & \\
130 & r8 or xmm2 & & \\ 132 & r9 or xmm3 & \mrrbrace{4}{spill area} & \\
131 & rdx or xmm1 & & \\ 133 & r8 or xmm2 & & \\
132 & rcx or xmm0 & & \\ 134 & rdx or xmm1 & & \\
133 \hhline{~-~~} 135 & rcx or xmm0 & & \\
134 & return address & & \\ 136 \hhline{~-~~}
135 \hhline{~=~~} 137 & return address & & \\
136 local data & & & \mrrbrace{3}{current frame} \\ 138 \hhline{~=~~}
137 \hhline{~-~~} 139 register save area & & & \mrrbrace{4}{current frame} \\
138 parameter area & & & \\ 140 \hhline{~-~~}
139 \hhline{~-~~} 141 local data & & & \\
140 & \vdots & & \\ 142 \hhline{~-~~}
141 \hhline{~-~~} 143 parameter area & & & \\
144 \hhline{~-~~}
145 & \vdots & & \\
142 \end{tabular} 146 \end{tabular}
143 \caption{Stack layout on x64 Microsoft platform} 147 \caption{Stack layout on x64 Microsoft platform}
144 \end{figure} 148 \end{figure}
145 149
146 150
189 \item integer/pointer parameters \textgreater\ 64 bit are passed via 2 registers 193 \item integer/pointer parameters \textgreater\ 64 bit are passed via 2 registers
190 \item if callee takes address of a parameter, number of used xmm registers is passed silently in al (passed number mustn't be 194 \item if callee takes address of a parameter, number of used xmm registers is passed silently in al (passed number mustn't be
191 exact but an upper bound on the number of used xmm registers) 195 exact but an upper bound on the number of used xmm registers)
192 \item stack is always 16byte aligned - since return address is 64 bits in size, stacks with an odd number of parameters are 196 \item stack is always 16byte aligned - since return address is 64 bits in size, stacks with an odd number of parameters are
193 already aligned 197 already aligned
198 \item no spill area is used on stack, iterating over varargs requires a specific va\_list implementation
194 \end{itemize} 199 \end{itemize}
195 200
196 201
197 \paragraph{Return values} 202 \paragraph{Return values}
198 203
205 \end{itemize} 210 \end{itemize}
206 211
207 212
208 \paragraph{Stack layout} 213 \paragraph{Stack layout}
209 214
210 Stack frame is always 16-byte aligned. Note that there is no spill area. 215 Stack frame is always 16-byte aligned.
216 % verified/amended: TP nov 2019 (see also doc/disas_examples/x64.sysv.disas)
211 Stack directly after function prolog:\\ 217 Stack directly after function prolog:\\
212 218
213 \begin{figure}[h] 219 \begin{figure}[h]
214 \begin{tabular}{5|3|1 1} 220 \begin{tabular}{5|3|1 1}
215 \hhline{~-~~} 221 & \vdots & & \\
216 & \vdots & & \\ 222 \hhline{~=~~}
217 \hhline{~=~~} 223 register save area & \hspace{4cm} & & \mrrbrace{6}{caller's frame} \\
218 local data & \hspace{4cm} & & \mrrbrace{5}{caller's frame} \\ 224 \hhline{~-~~}
219 \hhline{~-~~} 225 local data (with padding) & & & \\
220 \mrlbrace{3}{parameter area} & \ldots & \mrrbrace{3}{stack parameters} & \\ 226 \hhline{~-~~}
221 & \ldots & & \\ 227 \mrlbrace{3}{parameter area} & arg n-1 & \mrrbrace{3}{stack parameters} & \\
222 & \ldots & & \\ 228 & \ldots & & \\
223 \hhline{~-~~} 229 & arg 6 & & \\
224 & return address & & \\ 230 \hhline{~-~~}
225 \hhline{~=~~} 231 & return address & & \\
226 local data & & & \mrrbrace{3}{current frame} \\ 232 \hhline{~=~~}
227 \hhline{~-~~} 233 register save area & & & \mrrbrace{4}{current frame} \\
228 parameter area & & & \\ 234 \hhline{~-~~}
229 \hhline{~-~~} 235 local data & & & \\
230 & \vdots & & \\ 236 \hhline{~-~~}
231 \hhline{~-~~} 237 parameter area & & & \\
238 \hhline{~-~~}
239 & \vdots & & \\
232 \end{tabular} 240 \end{tabular}
233 \caption{Stack layout on x64 System V (Linux/*BSD)} 241 \caption{Stack layout on x64 System V (Linux/*BSD)}
234 \end{figure} 242 \end{figure}
235 243