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comparison doc/manual/callconvs/callconv_arm32.tex @ 649:0909837648d2

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doc: - RISC-V64 callconv appendix - some typo fixes and cleanup
author Tassilo Philipp
date Thu, 22 Feb 2024 17:49:07 +0100
parents fc614cb865c6
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648:a54e1f04588f 649:0909837648d2
41 41
42 \paragraph{\product{dyncall} support} 42 \paragraph{\product{dyncall} support}
43 43
44 Currently, the \product{dyncall} library supports the ARM and THUMB mode of the 44 Currently, the \product{dyncall} library supports the ARM and THUMB mode of the
45 ARM32 family (ATPCS \cite{ATPCS}, EABI \cite{armeabi}, the ARM hard-float 45 ARM32 family (ATPCS \cite{ATPCS}, EABI \cite{armeabi}, the ARM hard-float
46 (armhf) \cite{armeabi} varian, as well as Apple's calling convention based on 46 (armhf) \cite{armeabi} variant, as well as Apple's calling convention based on
47 the ATPCS), excluding manually triggered ARM-THUMB interworking calls.\\ 47 the ATPCS), excluding manually triggered ARM-THUMB interworking calls.\\
48 Also supported is armhf, a calling convention with register support to pass 48 Also supported is armhf, a calling convention with register support to pass
49 floating point numbers. FPA and the VFP (scalar mode) procedure call standards, 49 floating point numbers. FPA and the VFP (scalar mode) procedure call standards,
50 as well as some instruction sets accelerating DSP and multimedia application 50 as well as some instruction sets accelerating DSP and multimedia application
51 like the ARM Jazelle Technology (direct Java bytecode execution, providing 51 like the ARM Jazelle Technology (direct Java bytecode execution, providing